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Application of the Logic-in-Memory approach to a RISC-V processor using emerging technologies

Gianluca Goti

Application of the Logic-in-Memory approach to a RISC-V processor using emerging technologies.

Rel. Fabrizio Riente, Marco Vacca, Andrea Coluccio. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2022

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In recent years, many efforts have been spent on research on emerging technologies applied to memories. Many different devices are present on the market, each of them with its peculiarity but in general, as a rule of thumb, if the storage capacity increases the speed decreases. Furthermore, the standard technology suffers from physical and technological limitations. Novel technologies try to overcome such limitations, Racetrack technology seems to be a good candidate to satisfy at the same time the requirements of speed and storage capacity. Racetrack is essentially a ferromagnetic wire where bits are retained by exploiting the magnetization direction. Bits are accessed and modified only through dedicated ports, thus this requires bit alignment to the access ports by means of shift operations along the ferromagnetic structure. Studies on this technology showed interesting performances in both access latency and storage capacity. Another very important issue in modern Electronics is the so called Memory-wall. Today’s architectures are capable of astonishing performances but the exchange with the memory slows down the overall performance. It is in this context that the Logic-in-Memory paradigm takes place. The idea is to create completely new architectures able to partially or even totally perform computations directly in memory embedding logic elements within the memory. This limits the exchange of data back and for, increasing the system performance. This Thesis work focused on the application of the Logic-in-Memory paradigm to the emerging Racetrack technology. This new architecture was applied to an open computing system named RI5CY already provided with a LiM architecture. The proposed architecture aims to offer an open and configurable Logic-in-Memory platform in which multiple types of memory can be tested. In addition, this work proposes a working RTL model of a Racetrack memory with LiM capabilities with performances comparable to the original LiM system. Furthermore, this Thesis tries to give some ideas on new possible internal organizations for the Racetrack memory. Simulations showed that the new Racetrack memory seems to be a good candidate to replace the standard technology. Combining Racetrack with the Logic-in-Memory paradigm should be an interesting solution to overcome the memory-wall problem and limitations due to standard memory technologies.

Relators: Fabrizio Riente, Marco Vacca, Andrea Coluccio
Academic year: 2022/23
Publication type: Electronic
Number of Pages: 124
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: UNSPECIFIED
URI: http://webthesis.biblio.polito.it/id/eprint/24675
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