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A novel miniaturised CMOS architecture for on-chip data and clock recovery in Wireless RF ASK-demodulators

Matilde Cerbai

A novel miniaturised CMOS architecture for on-chip data and clock recovery in Wireless RF ASK-demodulators.

Rel. Danilo Demarchi, Gian Luca Barbruni, Sandro Carrara, Paolo Motto Ros. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2022

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Wireless power and data transmission is an efficient method to develop miniaturised and highly distributed neural interfaces. Amplitude Shift Keying (ASK) modulation is commonly used in the case of ultra-miniaturised implants. Over the years, several ASK-based Clock Data Recovery (CDR) architectures have been proposed with different objectives, such as: increasing the data rate, decreasing the silicon area and reducing the power consumption. The state-of-the-art includes: synchronous architectures mainly relied on complex Phase Locked Loop (PLL) based circuits or asynchronous systems with the need of on-chip oscillators. This master’s thesis is a part of an ambitious project focused on reverting blindness, carried out in the Bio/CMOS Interfaces Group at Integrated Circuits Laboratory (EPFL, Neuchatel). The idea is to develop an innovative implantable cortical visual prosthesis based on ultra-miniaturised, wireless, individually addressable and free-floating CMOS implants for precise intracortical neurostimulation. The present work aims to create a miniaturised and low-power architecture that guarantees both data and clock recovery starting from an ASK-modulated signal. The newly proposed CDR architecture consists mainly of an RF ASK demodulator and a clock recovery system, both implemented in Cadence using TSMC-180 nm CMOS technology. The demodulator receives the wirelessly transmitted ASK-modulated signal at 433.92 MHz and generates the relative digital waveform. The latter is reconstructed for a data rate as high as 6 Mbps and a modulation index in the range of 9-30%. Two CDR versions have been implemented. In the first one, a frequency multiplier receives a precise train of pulses from the demodulator output to generate the clock. In the second case, the clock is directly extracted from the demodulated digital signal, which is set with a higher frequency than the data. For both implementations, a control block is introduced to pull up the clock and save it in a memorisation structure. After clock memorisation, data are ready to be sampled synchronously. Both the demodulated clock and data are serialised; thus, a transmission protocol is defined to differentiate between them. Simulations validate the functionality of the two entire architectures. The second solution outperforms the first one both in terms of area and power consumption. The whole CDR architecture occupies 1500 μm2 and consumes 15 μW while operating with a clock data rate of 6 Mbps. The newly proposed solution is, therefore, a valid alternative to the state-of-the-art, especially in RF applications. In the future, the demodulator can be optimised to work at a higher data rate while consuming even less power. Area reduction is possible considering smaller technology nodes, such as 90 nm.

Relators: Danilo Demarchi, Gian Luca Barbruni, Sandro Carrara, Paolo Motto Ros
Academic year: 2022/23
Publication type: Electronic
Number of Pages: 112
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
URI: http://webthesis.biblio.polito.it/id/eprint/24662
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