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Design and silicon implementation of virtual voltage reference circuits

Gabriel Steven Romero Rondon

Design and silicon implementation of virtual voltage reference circuits.

Rel. Paolo Stefano Crovetti, Roberto Rubino. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2022

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Current constraints on System-on-chip (SoC) circuits push towards minimization of both area and power consumption. Typical SoC utilises bandgap voltage references to provide a reference voltage to the circuits in the SoC. However, the area and power consumed by the elements that compose a bandgap reference are not suitable for the requirements of nowadays circuits. In line with the common trend of implementing analog functions using circuits mainly composed of digital blocks, virtual voltage references emerge as the alternative to the usual analog voltage reference solution. Moreover, their implementation is still connected since the concept of virtual voltage reference originates from the generalization of the principles used in the design of bandgap voltage references. This work presents the design of a virtual voltage reference circuit. For this particular implementation, the selected primitives do not correspond to the typical voltage and current variables. Instead, the time domain behaviour of a physical reference is used as the main parameter in this circuit. Different alternatives for the physical reference of the circuit are discussed, along with the theoretical model of the chosen reference. Besides, several modelling approaches are presented during the discussion of enhancing the supply voltage variation. This document also highlights the advantages of relying on the virtual voltage reference algorithm to achieve more promising line regulation results. Furthermore, an analysis of the appropriate number of bits for achieving a suitable voltage reference is performed for this implementation of the virtual voltage reference. The circuit layout is accomplished in a 180-nm CMOS standard technology. The possibilities for achieving temperature compensation of the reference voltage have been analysed in the range from 0°C to 100°C. The line regulation was measured using pre-layout simulations, showing a line regulation below 0.2 %/V. This solution is compared with the previous implementation of the virtual voltage reference and state-of-the-art analog solutions. Such comparison underlines the advantages and problems observed in the virtual voltage reference when analogized with other solutions.

Relators: Paolo Stefano Crovetti, Roberto Rubino
Academic year: 2022/23
Publication type: Electronic
Number of Pages: 106
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: Politecnico di Torino
URI: http://webthesis.biblio.polito.it/id/eprint/24638
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