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Digital design flow for the ADC controllers of an Analog On Top System on Chip for Power Management Integrated Circuits(PMIC)

Rita Caporale

Digital design flow for the ADC controllers of an Analog On Top System on Chip for Power Management Integrated Circuits(PMIC).

Rel. Maurizio Martina. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2022


Nowadays, portable devices have become increasingly widespread thanks to both significant technological scaling and for efficient battery life management. In this domain, Power Management Integrated Circuit (PMIC) plays a key role. It is intended for several functions ranging from charging, monitoring battery status, and applying voltage scaling according to the operating state the device is in. Modern PMICs represent true System-on-Chips (SoCs): in fact, in order to handle the increasing complexity of the analog circuitry, the digital component results in an increasing number of IPs. In this thesis, a dedicated ADC Controller used to monitoring various input/output measurement for PMIC application is presented. The main goal of this thesis is to expose the grant I gave during experience in STMicroelectronics DAC division in developing additional features on already existing ADC Controller. In order to do that, both the concepts learned during the course of study, using as starting point for stepping into this experience, and those learned during the project are essential to best introduce the work done. In the first one, a brief introduction of SoCs and a summary description of their internal structure at the system level is exposed in order to give a global view of the system. In the second section, an important aspect is covered: the design flow used within ST's DAC division. Certainly, knowing and following a well-structured design flow is necessary in complex systems where the customer demands time to market and costs that are difficult to meet. The third and fourth sections, on the other hand, deal with more technical topics and expose in varying degrees of detail the building blocks that an analog-to-digital conversion chain requires. Particularly, third section covers some implementation details concerning the analog part of analog to digital conversion world, particularly ADC block. The key concepts of analog to digital conversion chain are exposed including: reason why the conversion chain is used, which are the main blocks which are usually used in conversion chain, principles of ADC operation, parameters and proposal of various architectures with consequent analysis on the advantages and disadvantages for each. The last, but not least, chapter exposes the case study ADC Controller digital block. It is a block capable of driving ADC and other analog control signals to perform conversions on any selected channel. Particularly, new features have been added in the existing block to be compliant with system requirement, such as a low power strategy and HW structures to facilitate data processing by the FW for power calculation, calibration, and other purposes.

Relators: Maurizio Martina
Academic year: 2022/23
Publication type: Electronic
Number of Pages: 103
Additional Information: Tesi secretata. Fulltext non presente
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: STMicroelectronics
URI: http://webthesis.biblio.polito.it/id/eprint/24541
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