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Test and characterization of an integrated circuit implementing a low-energy compressed-sensing based acquisition system

Francesco Trinca

Test and characterization of an integrated circuit implementing a low-energy compressed-sensing based acquisition system.

Rel. Gianluca Setti, Fabio Pareschi, Carmine Paolino. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2022

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Latest demand for advanced IC solutions in industrial, wireless or biomedical field, has lead to a growing interest for innovation in data converters. Physical signals, such as audio, radio or image signals, belonging to the real world, have to be converted into numerical values, with the intention of process and store them. Analog-to-Digital converters represent the interface between the analog domain and the digital domain. In modern applications regarding the biomedical field, energy and area consumption have become critical requirements for an ADC. Converters adopted for acquire bio-signals, such as ECG, must have low power consumption and low area, in order to allow the highest level of integration, as well as long battery life in case of portable devices. For this reason, signal processing has gained an increasing interest among the research community. Compressed sensing is a signal processing technique for efficiently acquire and reconstruct an analog signal from the energy consumption point of view. The starting point of this thesis is an already developed chip which is essentially a SAR ADC with CS capabilities. Every time a new IC is designed, the importance to test and characterize it is crucial. The aim of this work is to test and characterize the chip, and so the ADC, designing an ad-hoc testing platform, with the intention of provide control signals for the chip, regulated supply voltages and obviously, the analog input signals. First of all, an ADC must be characterized by means of the common figures of merit, through simulations, in order to verify if its performances meet the specifications of the project. Subsequently, having the physical chip, it is significant to test its functionality. To do this, a deep knowledge of both logic and analog part of the chip under test is needed, in order to design a measurement set up. The latter has been designed to host the IC, allowing the device characterization and testing.

Relators: Gianluca Setti, Fabio Pareschi, Carmine Paolino
Academic year: 2021/22
Publication type: Electronic
Number of Pages: 135
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: UNSPECIFIED
URI: http://webthesis.biblio.polito.it/id/eprint/23521
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