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Ultra-Low-Power acoustic sensor frontend a digital transconductance amplifier approach

Fabio Bani

Ultra-Low-Power acoustic sensor frontend a digital transconductance amplifier approach.

Rel. Paolo Stefano Crovetti, Taekwang Jang. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2022


IoT devices operate in constrained conditions, with limited supply voltage and power and, depending on the application, with set requirements also on bandwidth. On the other hand, noise is a prime concern because it puts a lower bound on the dynamic range. To balance these constraints and evaluate the most efficient front-end, the Noise Efficiency Factor (NEF) has been proposed, in effect, judging the efficiency of the amplifier based on the current consumption, bandwidth and input referred noise. Acoustic band front-ends are especially sensitive to noise because of their wide band (20Hz-22kHz) but also because of the need to sense low signal levels. Recent works are based on the classical LNA+VGA+ADC topology, leading to complexity and high energy consumption by the ADC. To eliminate the need for an explicit ADC, a digital-based OTA (DIGOTA) approach has been studied in this work. For the first time we study the DIGOTA implementation in the wide acoustic band. From a theoretical perspective, we provide an overview of DIGOTA, we analyse in detail its noise sources of DIGOTA, adding to the previous works the jitter noise of its internal components. We choose to proceed with CMOS gates due to their good performance and robustness to PVT variations. On the design stage, by evaluating leakage current, we determine the appropriate gf22 transistor version for the implementation, which, turns out to be uhvt. Then, by system-level simulations, we determine the appropriate supply voltage to stay in sub--μW power consumption, which turns out to be the range 0.4-0.6V. This range is fully capable of giving us a bandwidth of 22kHz and more. We reduce the logic redundancy to the minimum possible through equivalent logic. Then, we try to size each gate appropriately, guaranteeing undistorted digital signals for the backend, bearing in mind the implications on the current consumption and ultimately, on the NEF. In parallel with the internal design of DIGOTA, special care must be given to its external components needed to guarantee uniform and controlled gain and bandwidth, namely the feedback capacitors and resistor. These components have size constraints. For the capacitors, they can reasonably be at the pF range, with no more than 30pF in total. As for the resistor, it is impossible to implement it with the classical approach, obviously because of size. Therefore we implement it with the most stable pseudoresistor configuration. As a last step, the 0.4V and 0.5V versions of DIGOTA are tested as a system for NEF achieving competitive results of less than 1.5. We note that in this figure it's included also the quantization noise, previously excluded from consideration in other works of ultra-low-power amplifiers. Finally, the work suggests issues of focus on how the DIGOTA can be further improved and suggestions on how to integrate it with the digital backend.

Relators: Paolo Stefano Crovetti, Taekwang Jang
Academic year: 2021/22
Publication type: Electronic
Number of Pages: 71
Additional Information: Tesi secretata. Fulltext non presente
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Ente in cotutela: ETH Z├╝rich (SVIZZERA)
Aziende collaboratrici: ETH Zurich
URI: http://webthesis.biblio.polito.it/id/eprint/22870
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