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Model Based SW Design and Integration of a Vehicle Managment Unit's Control Architecture for an Electric Vehicle Retrofit

Andrea Gaudiano

Model Based SW Design and Integration of a Vehicle Managment Unit's Control Architecture for an Electric Vehicle Retrofit.

Rel. Stefano Carabelli. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2022


The following thesis project comes from the internship experience carried out at Brain Technologies s.r.l for the EVERGRIN project. The aim of the project is to develop a software and hardware product, following a new approach, able to simplify the conversion of a thermal engine vehicle into an electric one. The methodology chosen to develop this project is the Extended V-Cycle, a modified version of the V-Cycle for the automotive sector. The retrofit kit consists of core subsystems such as the Power Box, the Battery Pack and the VMU which is responsible for the e-Powertrain control and e-Powertrain/Vehicle interface. The VMU is a smart device that allows a quick configurability of a new electric car, but which can also be adapted to an existing vehicle, as part of a retrofit activity. The main goal in fact is to create a malleable software architecture which can quickly adapt to any hardware application. The design phase has started from the phase 1 of the V-cycle which consists of the system requirement definition. The drafting of this requirements was carried out following the ISO29148 standard. The requirements have been divided into functional groups, focusing more on traction, charging and parking functions. For the phase 2 of system design, a Model Based Approach has been adopted in MATLAB/ Simulink environment. A particular focus was given to the MTM (modular technical model). The VMU control logic and the I/O interfaces have been modelled. After the code has been generated with embedded coder, it has been implemented and tested on a Rapid Prototyping tool. In this phase, some real components of the car were integrated into the logic, such as the accelerator pedal and the key block. When this phase is successful the code is considered to be verified and can be implemented on the target hardware. Otherwise it is necessary to return to the previous step and make the necessary changes to correct the model. The phase 2.3 required the choice of the VMU. The chosen product is the HY-TTC 32s made by TTControl, as it respects the required technical and safety characteristics. The phase 3.0 consists in the realization of the baseline software architecture for the VMU and the integration of the control logic developed in the previous phases within the control unit. For the implementation of the software of the VMU the program language used was C. In the preliminary phase two activities were carried out, the first was based on analyzing the functioning of the CAN network and the format of the CAN frames travelling on the bus, while the second was based on verifying some characteristics of the I/O channels of the VMU. The main work regarding software development was to implement new features for the baseline software architecture which is already equipped, thanks to a previous inherited job, with a task scheduling and overrun system. The first feature that was implemented made it possible to create a system for Real-time tuning parameter through the CAN network, it was therefore necessary to implement a mechanism that would allow to read messages sent on the CAN bus. This function allows, in a configuration phase, to modify the vehicle parameters in real-time and to observe in real time how it responds. Also, a system that allows the VMU to enter into an energy-saving mode has been created. The features of the baseline software architecture and the development has been tested, as a whole, with a simple example, an RC filter, in order to verify the correctness of the development procedure.

Relators: Stefano Carabelli
Academic year: 2021/22
Publication type: Electronic
Number of Pages: 9
Additional Information: Tesi secretata. Fulltext non presente
Corso di laurea: Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering)
Classe di laurea: New organization > Master science > LM-32 - COMPUTER SYSTEMS ENGINEERING
Aziende collaboratrici: Brain technologies
URI: http://webthesis.biblio.polito.it/id/eprint/22789
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