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Digital interface for Advanced mixed-signal IP suitable for GaN power conversion

Michelangelo Orabona

Digital interface for Advanced mixed-signal IP suitable for GaN power conversion.

Rel. Maurizio Martina, Juri Giovannone. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2022

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In modern power converter the goal is not only to get high efficiency, achievable by using the GaN technology, but also the possibility of reconfigurability of the control stage. To this aim digital control loop has started to be used which among the many advantages in terms of integrability, speed and compatibility with GaN achievable performance, can also integrate self-adjustment and testing circuitry being also reconfigurable based on the application. This boosts the efficiency of the overall converter, reducing cost and size also considering the possibility to integrate a complete power system, with control logic, signal processing stage and power stage on a single System-On-Chip SoC thanks to the BCD process used by STMicrolectronics. Since classic PWM scheme are not well suited to get time resolution up to tenth of picoseconds this Thesis introduces a new approach based on the realization of a hybrid solution based on a Programmable Delay Unit or Delay Locked Loop to obtain the desired precision on digital PWM signal. The thesis is divided into three main sections: after an introduction on the Smart Power technology and the BCD process capability, the background section, composed by the first three chapter, introduces briefly the concept required to analyze and design a classic converter (focusing on the buck, boost, and buck-boost converters), starting from the topology to the study of the control loop transfer function. The fourth chapter focuses on the followed flow to implement the digital control loop, from RTL to the final verilog netlist also integrating the Design for Testability functions. The following section, composed by chapter five and six, describes the implementation of the PDU digital control section, describing the challenge required to meet all the timing performance requirements and to get the final synthesized circuit after the DFT insertion. The last two Chapter describe the obtained results out of the mixed signal simulation, describing how to set the simulation environment, commenting the obtained results and giving conclusion the overall implementation.

Relators: Maurizio Martina, Juri Giovannone
Academic year: 2021/22
Publication type: Electronic
Number of Pages: 117
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: STMicroelectronics
URI: http://webthesis.biblio.polito.it/id/eprint/22779
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