#!/bin/bash
# \
exec vsim -64 -do "$0"
echo "arguments"
#echo "$0"
set TB_TEST $::env(TB_TEST)
echo "TB_TEST"
echo $TB_TEST
set VSIM_FLAGS    "-GTEST=\"$TB_TEST\""

set TB            tb
set MEMLOAD       "PRELOAD"

source ./tcl_files/config/vsim.tcl

#do ./tcl_files/wave.do

#add wave /tb/top_i/core_region_i/CORE/RISCV_CORE/*
#add wave /tb/top_i/core_region_i/CORE/RISCV_CORE/id_stage_i/registers_i/mem

#deposit tutti i registri
#for {set i 1} {$i < 32} {incr i} {
#	for {set j 0} {$j < 32} {incr j} {
#		force -deposit sim:/tb/top_i/core_region_i/CORE/RISCV_CORE_GATE/id_stage_i_registers_i/mem_${i}__${j}_ 1'h0	
#	}	 
#}

#force -deposit sim:/tb/top_i/core_region_i/CORE/RISCV_CORE_GATE/id_stage_i_registers_i/wdata_a_i 32'h00000000 0


#add wave -position insertpoint  \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/is_compressed_id
#add wave -position insertpoint  \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/id_valid
#add wave -position insertpoint  \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/is_decoding
#add wave -position insertpoint  \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/id_stage_i_pipe_flush_dec
#add wave -position insertpoint  \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/id_stage_i_mret_insn_dec
#add wave -position insertpoint  \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/id_stage_i_ecall_insn_dec
#add wave -position insertpoint  \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/id_stage_i_ebrk_insn
#add wave -position insertpoint  \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/operand_a_fw_id \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/operand_b_fw_id \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/alu_operand_c \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/alu_operand_b
#add wave -position insertpoint  \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/id_stage_i_decoder_i/reg_fp_a_o \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/id_stage_i_decoder_i/reg_fp_b_o \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/id_stage_i_decoder_i/reg_fp_c_o \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/id_stage_i_decoder_i/reg_fp_d_o
#add wave -position insertpoint  \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/id_stage_i_ex_valid_i
#add wave -position insertpoint  \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/regfile_alu_waddr_ex
#add wave -position insertpoint  \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/regfile_alu_we_ex
#add wave -position insertpoint  \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/regfile_alu_wdata_fw
#add wave -position insertpoint  \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/branch_in_ex
#add wave -position insertpoint  \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/id_stage_i_wb_ready_i
#add wave -position insertpoint  \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/ex_stage_i_regfile_waddr_lsu
#add wave -position insertpoint  \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/ex_stage_i_regfile_we_lsu
#add wave -position insertpoint  \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/ex_stage_i_lsu_rdata_i
#add wave -position insertpoint  \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/imm_u_type \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/imm_uj_type \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/imm_i_type \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/imm_iz_type \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/imm_s_type \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/imm_sb_type \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/imm_s2_type \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/imm_s3_type \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/imm_vs_type \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/imm_vu_type \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/imm_shuffle_type \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/imm_z_type
#add wave -position insertpoint  \
#sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/instr_rdata_id
#

log -r *
add wave -divider CLK -color green -position insertpoint  \
sim:/tb/s_clk
add wave -divider INPUT  -color yellow -position insertpoint  \
sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/ex_stage_i_alu_i/U1718/A1
#add wave -color red -position insertpoint  \
#sim:/tb/top_i_f/core_region_i/CORE/RISCV_CORE/ex_stage_i_alu_i/U1718/A1
add wave -divider OUTPUT -color yellow -position insertpoint  \
sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/instr_req_o
#add wave -color red -position insertpoint  \
#sim:/tb/top_i_f/core_region_i/CORE/RISCV_CORE/instr_req_o
add wave -color yellow -position insertpoint  \
sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/data_req_o
#add wave -color red -position insertpoint  \
#sim:/tb/top_i_f/core_region_i/CORE/RISCV_CORE/data_req_o
add wave -color yellow -position insertpoint  \
sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/data_we_o
#add wave -color red -position insertpoint  \
#sim:/tb/top_i_f/core_region_i/CORE/RISCV_CORE/data_we_o
add wave -color yellow -position insertpoint  \
sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/instr_addr_o
#add wave -color red -position insertpoint  \
#sim:/tb/top_i_f/core_region_i/CORE/RISCV_CORE/instr_addr_o
add wave -color yellow -position insertpoint  \
sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/data_addr_o
#add wave -color red -position insertpoint  \
#sim:/tb/top_i_f/core_region_i/CORE/RISCV_CORE/data_addr_o
add wave -color yellow -position insertpoint  \
sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/data_wdata_o
#add wave -color red -position insertpoint  \
#sim:/tb/top_i_f/core_region_i/CORE/RISCV_CORE/data_wdata_o
add wave -color yellow -position insertpoint  \
sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/data_be_o
#add wave -color red -position insertpoint  \
#sim:/tb/top_i_f/core_region_i/CORE/RISCV_CORE/data_be_o
#

#set forbiddenTime 0
#
#when -fast {/top_i/core_region_i/CORE/RISCV_CORE/ex_stage_i_alu_i/U1718/A1'event and /top_i/core_region_i/CORE/RISCV_CORE/ex_stage_i_alu_i/U1718/A1 = 1'h0} {
#        uivar forbiddenTime
#        if {$now != $forbiddenTime} {
#                force -freeze /tb/top_i/core_region_i/CORE/RISCV_CORE/ex_stage_i_alu_i/U1718/A1 1'h1 -cancel { 44 ns }
#                set forbiddenTime [expr {$now + 44}]
#        }
#}


#when -fast { /tb/top_i/core_region_i/CORE/RISCV_CORE/ex_stage_i_alu_i/U1718/A1'event and /tb/top_i/core_region_i/CORE/RISCV_CORE/ex_stage_i_alu_i/U1718/A1 = 1'h0 } { 
#		force -freeze sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/ex_stage_i_alu_i/U1718/A1 1'h1 0
#		force -deposit sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/ex_stage_i_alu_i/U1718/A1 1'h0 {44 ns}  
#}

#when -fast { s_clk'event and s_clk = 1'h0 } {
#	force -freeze /tb/top_i/core_region_i/CORE/RISCV_CORE/ex_stage_i_alu_i/U1718/A1 [examine /tb/top_i/core_region_i/CORE/RISCV_CORE/ex_stage_i_alu_i/U1718/A1] -cancel { 30 ns }
#	force -freeze sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/n_3_net__2_ [examine sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/n_3_net__2_] -cancel { 50 ns }
#}
	
#	if {[/tb/top_i/core_region_i/CORE/RISCV_CORE/ex_stage_i_alu_i/U1718/A1 = 1'h1]} {
#		force -freeze sim:/tb/top_i/core_region_i/CORE/RISCV_CORE/ex_stage_i_alu_i/U1718/A1 1'h0 -cancel { 44 ns }  

 

vcd dumpports /tb/top_i/core_region_i/CORE/RISCV_CORE/* -file tmax/dumpports_rtl.riscv_core.vcde -unique
 
