# source tcl_files/run.tcl
# arguments
# TB_TEST
# 
# vsim -quiet tb -L pulpino_lib -L axi_node_lib -L apb_node_lib -L axi_mem_if_DP_lib -L axi_spi_slave_lib -L axi_spi_master_lib -L apb_uart_sv_lib -L apb_gpio_lib -L apb_event_unit_lib -L apb_spi_master_lib -L fpu_lib -L apb_pulpino_lib -L apb_fll_if_lib -L core2axi_lib -L apb_timer_lib -L axi2apb_lib -L apb_i2c_lib -L zero_riscy_lib -L axi_slice_dc_lib -L riscv_lib -L riscv_lib_gate -L apb_uart_lib -L axi_slice_lib -L adv_dbg_if_lib -L apb2per_lib "+nowarnTRAN" "+nowarnTSCALE" "+nowarnTFMPC" "+MEMLOAD=PRELOAD" -t ps -voptargs="+acc -suppress 2103" -GTEST="" -gRISCY_RV32F=0 -gZERO_RV32E=0 -gZERO_RV32M=0 -gUSE_ZERO_RISCY=0 
# Start time: 00:29:14 on Mar 02,2022
# ** Note: (vsim-3812) Design is being optimized...
# ** Note: (vopt-143) Recognized 1 FSM in architecture body "uart_receiver(rtl)".
# ** Note: (vopt-143) Recognized 1 FSM in architecture body "uart_transmitter(rtl)".
# ** Note: (vopt-143) Recognized 2 FSMs in architecture body "apb_uart(rtl)".
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_multiplexer.sv(49): (vopt-13314) Defaulting port 'IN_DATA' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//rtl/axi_node_intf_wrap.sv(34): (vopt-13314) Defaulting port 'start_addr_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//rtl/axi_node_intf_wrap.sv(35): (vopt-13314) Defaulting port 'end_addr_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Note: (vopt-143) Recognized 1 FSM in module "spi_master_rx(fast)".
# ** Note: (vopt-143) Recognized 1 FSM in module "i2c_eeprom_model(fast)".
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_AR_allocator.sv(56): (vopt-13314) Defaulting port 'arid_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_AR_allocator.sv(57): (vopt-13314) Defaulting port 'araddr_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_AR_allocator.sv(58): (vopt-13314) Defaulting port 'arlen_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_AR_allocator.sv(59): (vopt-13314) Defaulting port 'arsize_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_AR_allocator.sv(60): (vopt-13314) Defaulting port 'arburst_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_AR_allocator.sv(62): (vopt-13314) Defaulting port 'arcache_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_AR_allocator.sv(63): (vopt-13314) Defaulting port 'arprot_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_AR_allocator.sv(64): (vopt-13314) Defaulting port 'arregion_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_AR_allocator.sv(65): (vopt-13314) Defaulting port 'aruser_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_AR_allocator.sv(66): (vopt-13314) Defaulting port 'arqos_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Note: (vopt-143) Recognized 2 FSMs in module "apb_spi_master(fast)".
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_BW_allocator.sv(59): (vopt-13314) Defaulting port 'bid_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_BW_allocator.sv(60): (vopt-13314) Defaulting port 'bresp_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_BW_allocator.sv(61): (vopt-13314) Defaulting port 'buser_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Note: (vopt-143) Recognized 1 FSM in module "axi_BW_allocator(fast)".
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_address_decoder_AR.sv(59): (vopt-13314) Defaulting port 'START_ADDR_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_address_decoder_AR.sv(60): (vopt-13314) Defaulting port 'END_ADDR_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_address_decoder_AR.sv(61): (vopt-13314) Defaulting port 'enable_region_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_response_block.sv(62): (vopt-13314) Defaulting port 'rid_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_response_block.sv(63): (vopt-13314) Defaulting port 'rdata_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_response_block.sv(64): (vopt-13314) Defaulting port 'rresp_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_response_block.sv(66): (vopt-13314) Defaulting port 'ruser_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_response_block.sv(71): (vopt-13314) Defaulting port 'bid_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_response_block.sv(72): (vopt-13314) Defaulting port 'bresp_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_response_block.sv(73): (vopt-13314) Defaulting port 'buser_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_response_block.sv(123): (vopt-13314) Defaulting port 'START_ADDR_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_response_block.sv(124): (vopt-13314) Defaulting port 'END_ADDR_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_response_block.sv(125): (vopt-13314) Defaulting port 'enable_region_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/apb/apb_node/apb_node.sv(46): (vopt-13314) Defaulting port 'prdata_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/apb/apb_node/apb_node.sv(51): (vopt-13314) Defaulting port 'START_ADDR_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/apb/apb_node/apb_node.sv(52): (vopt-13314) Defaulting port 'END_ADDR_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_DW_allocator.sv(60): (vopt-13314) Defaulting port 'wdata_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_DW_allocator.sv(61): (vopt-13314) Defaulting port 'wstrb_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_DW_allocator.sv(63): (vopt-13314) Defaulting port 'wuser_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/adv_dbg_if/rtl/adbg_or1k_biu.sv(77): (vopt-13314) Defaulting port 'cpu_data_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/adv_dbg_if/rtl/adbg_top.sv(69): (vopt-13314) Defaulting port 'cpu_data_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Note: (vopt-143) Recognized 1 FSM in module "apb_fll_if(fast)".
# ** Note: (vopt-143) Recognized 1 FSM in module "i2c_master_byte_ctrl(fast)".
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/adv_dbg_if/rtl/adv_dbg_if.sv(36): (vopt-13314) Defaulting port 'cpu_data_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Note: (vopt-143) Recognized 1 FSM in module "generic_fifo(fast)".
# ** Note: (vopt-143) Recognized 1 FSM in module "generic_fifo(fast__1)".
# ** Note: (vopt-143) Recognized 1 FSM in module "generic_fifo(fast__2)".
# ** Note: (vopt-143) Recognized 1 FSM in module "generic_fifo(fast__3)".
# ** Note: (vopt-143) Recognized 1 FSM in module "generic_fifo(fast__4)".
# ** Note: (vopt-143) Recognized 1 FSM in module "generic_fifo(fast__5)".
# ** Note: (vopt-143) Recognized 1 FSM in module "generic_fifo(fast__6)".
# ** Note: (vopt-143) Recognized 1 FSM in module "generic_fifo(fast__7)".
# ** Note: (vopt-143) Recognized 1 FSM in module "generic_fifo(fast__8)".
# ** Note: (vopt-143) Recognized 1 FSM in module "generic_fifo(fast__9)".
# ** Note: (vopt-143) Recognized 1 FSM in module "generic_fifo(fast__10)".
# ** Note: (vopt-143) Recognized 1 FSM in module "generic_fifo(fast__11)".
# ** Note: (vopt-143) Recognized 1 FSM in module "sleep_unit(fast)".
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(74): (vopt-13314) Defaulting port 'slave_awid_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(75): (vopt-13314) Defaulting port 'slave_awaddr_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(76): (vopt-13314) Defaulting port 'slave_awlen_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(77): (vopt-13314) Defaulting port 'slave_awsize_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(78): (vopt-13314) Defaulting port 'slave_awburst_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(80): (vopt-13314) Defaulting port 'slave_awcache_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(81): (vopt-13314) Defaulting port 'slave_awprot_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(82): (vopt-13314) Defaulting port 'slave_awregion_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(83): (vopt-13314) Defaulting port 'slave_awuser_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(84): (vopt-13314) Defaulting port 'slave_awqos_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(90): (vopt-13314) Defaulting port 'slave_wdata_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(91): (vopt-13314) Defaulting port 'slave_wstrb_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(93): (vopt-13314) Defaulting port 'slave_wuser_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(109): (vopt-13314) Defaulting port 'slave_arid_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(110): (vopt-13314) Defaulting port 'slave_araddr_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(111): (vopt-13314) Defaulting port 'slave_arlen_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(112): (vopt-13314) Defaulting port 'slave_arsize_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(113): (vopt-13314) Defaulting port 'slave_arburst_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(115): (vopt-13314) Defaulting port 'slave_arcache_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(116): (vopt-13314) Defaulting port 'slave_arprot_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(117): (vopt-13314) Defaulting port 'slave_arregion_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(118): (vopt-13314) Defaulting port 'slave_aruser_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(119): (vopt-13314) Defaulting port 'slave_arqos_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(168): (vopt-13314) Defaulting port 'master_bid_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(169): (vopt-13314) Defaulting port 'master_bresp_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(170): (vopt-13314) Defaulting port 'master_buser_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(195): (vopt-13314) Defaulting port 'master_rid_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(196): (vopt-13314) Defaulting port 'master_rdata_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(197): (vopt-13314) Defaulting port 'master_rresp_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(199): (vopt-13314) Defaulting port 'master_ruser_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(240): (vopt-13314) Defaulting port 'cfg_START_ADDR_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(241): (vopt-13314) Defaulting port 'cfg_END_ADDR_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(242): (vopt-13314) Defaulting port 'cfg_valid_rule_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_node.sv(243): (vopt-13314) Defaulting port 'cfg_connectivity_map_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Note: (vopt-143) Recognized 1 FSM in module "adbg_axi_module(fast)".
# ** Note: (vopt-143) Recognized 1 FSM in module "adbg_axi_biu(fast)".
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/adv_dbg_if/rtl/adbg_or1k_module.sv(91): (vopt-13314) Defaulting port 'cpu_data_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Note: (vopt-143) Recognized 1 FSM in module "adbg_or1k_module(fast)".
# ** Note: (vopt-143) Recognized 1 FSM in module "spi_master_controller(fast)".
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_ArbitrationTree.sv(57): (vopt-13314) Defaulting port 'data_AUX_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_ArbitrationTree.sv(58): (vopt-13314) Defaulting port 'data_ID_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_ArbitrationTree.sv(57): (vopt-13314) Defaulting port 'data_AUX_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_ArbitrationTree.sv(58): (vopt-13314) Defaulting port 'data_ID_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_ArbitrationTree.sv(57): (vopt-13314) Defaulting port 'data_AUX_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_ArbitrationTree.sv(58): (vopt-13314) Defaulting port 'data_ID_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/apb/apb_node/apb_node_wrap.sv(40): (vopt-13314) Defaulting port 'start_addr_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/apb/apb_node/apb_node_wrap.sv(41): (vopt-13314) Defaulting port 'end_addr_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Note: (vopt-143) Recognized 1 FSM in module "axi2apb32(fast)".
# ** Note: (vopt-143) Recognized 1 FSM in module "axi_read_only_ctrl(fast)".
# ** Note: (vopt-143) Recognized 1 FSM in module "axi_read_only_ctrl(fast__1)".
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_BR_allocator.sv(60): (vopt-13314) Defaulting port 'rid_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_BR_allocator.sv(61): (vopt-13314) Defaulting port 'rdata_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_BR_allocator.sv(62): (vopt-13314) Defaulting port 'rresp_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_BR_allocator.sv(64): (vopt-13314) Defaulting port 'ruser_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Note: (vopt-143) Recognized 1 FSM in module "axi_BR_allocator(fast)".
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_mem_if_DP/axi_mem_if_SP.sv(48): (vopt-13314) Defaulting port 'WDATA_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_mem_if_DP/axi_mem_if_SP.sv(48): (vopt-13314) Defaulting port 'WDATA_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Note: (vopt-143) Recognized 1 FSM in module "i2c_master_bit_ctrl(fast)".
# ** Note: (vopt-143) Recognized 2 FSMs in module "spi_slave_axi_plug(fast)".
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(67): (vopt-13314) Defaulting port 'awid_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(68): (vopt-13314) Defaulting port 'awaddr_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(69): (vopt-13314) Defaulting port 'awlen_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(70): (vopt-13314) Defaulting port 'awsize_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(71): (vopt-13314) Defaulting port 'awburst_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(73): (vopt-13314) Defaulting port 'awcache_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(74): (vopt-13314) Defaulting port 'awprot_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(75): (vopt-13314) Defaulting port 'awregion_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(76): (vopt-13314) Defaulting port 'awuser_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(77): (vopt-13314) Defaulting port 'awqos_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(83): (vopt-13314) Defaulting port 'wdata_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(84): (vopt-13314) Defaulting port 'wstrb_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(86): (vopt-13314) Defaulting port 'wuser_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(93): (vopt-13314) Defaulting port 'arid_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(94): (vopt-13314) Defaulting port 'araddr_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(95): (vopt-13314) Defaulting port 'arlen_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(96): (vopt-13314) Defaulting port 'arsize_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(97): (vopt-13314) Defaulting port 'arburst_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(99): (vopt-13314) Defaulting port 'arcache_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(100): (vopt-13314) Defaulting port 'arprot_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(101): (vopt-13314) Defaulting port 'arregion_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(102): (vopt-13314) Defaulting port 'aruser_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_request_block.sv(103): (vopt-13314) Defaulting port 'arqos_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_address_decoder_AW.sv(64): (vopt-13314) Defaulting port 'START_ADDR_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_address_decoder_AW.sv(65): (vopt-13314) Defaulting port 'END_ADDR_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_address_decoder_AW.sv(66): (vopt-13314) Defaulting port 'enable_region_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Note: (vopt-143) Recognized 1 FSM in module "axi_address_decoder_AW(fast)".
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_AW_allocator.sv(56): (vopt-13314) Defaulting port 'awid_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_AW_allocator.sv(57): (vopt-13314) Defaulting port 'awaddr_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_AW_allocator.sv(58): (vopt-13314) Defaulting port 'awlen_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_AW_allocator.sv(59): (vopt-13314) Defaulting port 'awsize_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_AW_allocator.sv(60): (vopt-13314) Defaulting port 'awburst_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_AW_allocator.sv(62): (vopt-13314) Defaulting port 'awcache_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_AW_allocator.sv(63): (vopt-13314) Defaulting port 'awprot_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_AW_allocator.sv(64): (vopt-13314) Defaulting port 'awregion_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_AW_allocator.sv(65): (vopt-13314) Defaulting port 'awuser_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Warning: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//ips/axi/axi_node/axi_AW_allocator.sv(66): (vopt-13314) Defaulting port 'awqos_i' kind to 'var' rather than 'wire' due to default compile option setting of -svinputport=relaxed.
# ** Note: (vopt-143) Recognized 1 FSM in module "spi_slave_controller(fast)".
# ** Note: (vopt-143) Recognized 1 FSM in module "core2axi(fast)".
# ** Note: (vopt-143) Recognized 1 FSM in module "axi_write_only_ctrl(fast)".
# ** Note: (vopt-143) Recognized 1 FSM in module "axi_write_only_ctrl(fast__1)".
# ** Note: (vopt-143) Recognized 1 FSM in module "adbg_tap_top(fast)".
# //  ModelSim SE-64 2019.1 Jan  1 2019 Linux 3.10.0-1062.12.1.el7.x86_64
# //
# //  Copyright 1991-2019 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  ModelSim SE-64 and its associated documentation contain trade
# //  secrets and commercial or financial information that are the property of
# //  Mentor Graphics Corporation and are privileged, confidential,
# //  and exempt from disclosure under the Freedom of Information Act,
# //  5 U.S.C. Section 552. Furthermore, this information
# //  is prohibited from disclosure under the Trade Secrets Act,
# //  18 U.S.C. Section 1905.
# //
# ** Warning: (vsim-3852) Invalid override of parameter '/tb/TEST' whose value may no longer be modified.
#    Time: 0 ps  Iteration: 0  Instance: /tb File: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//tb/tb.sv
# ** Warning: (vsim-3770) Failed to find user specified function 'mem_init' in DPI C/C++ source files.
#    Time: 0 ps  Iteration: 0  Instance: /tb File: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//tb/tb.sv
# ** Warning: (vsim-3770) Failed to find user specified function 'mem_poll' in DPI C/C++ source files.
#    Time: 0 ps  Iteration: 0  Instance: /tb File: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//tb/tb.sv
# ** Warning: (vsim-3770) Failed to find user specified function 'mem_push' in DPI C/C++ source files.
#    Time: 0 ps  Iteration: 0  Instance: /tb File: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//tb/tb.sv
# ** Warning: (vsim-3770) Failed to find user specified function 'mem_push' in DPI C/C++ source files.
#    Time: 0 ps  Iteration: 0  Instance: /tb File: /auto/gmongelli/pulpino_environment/pulpino/vsim/..//tb/tb.sv
#  run -a
# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
#    Time: 0 ps  Iteration: 0  Instance: /tb/top_i/peripherals_i/apb_uart_i/UART_RXFF
# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
#    Time: 0 ps  Iteration: 0  Instance: /tb/top_i/peripherals_i/apb_uart_i/UART_TXFF
# Using MEMLOAD method: PRELOAD
# Using      ri5cy core
# [SPI] Enabling QPI mode
# [adv_dbg_if] AXI4 WRITE         32 burst @1a107008 for           4 bytes.
# Preloading memory
# Preloading instruction memory from slm_files/l2_stim.slm
# Preloading data memory from slm_files/tcdm_bank0.slm
# [TRACER] Output filename is: trace_core_00_0.log
# [SPI] Received 00000000
# [SPI] Test OK
# ** Note: $stop    : /auto/gmongelli/pulpino_environment/pulpino/vsim/..//tb/tb.sv(539)
#    Time: 695920 ns  Iteration: 0  Instance: /tb
# Break in Module tb at /auto/gmongelli/pulpino_environment/pulpino/vsim/..//tb/tb.sv line 539
# Stopped at /auto/gmongelli/pulpino_environment/pulpino/vsim/..//tb/tb.sv line 539
#  exit
# End time: 00:32:44 on Mar 02,2022, Elapsed time: 0:03:30
# Errors: 0, Warnings: 130
