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Implementation and evaluation of a Real-Time Multi-core Scheduler for Automotive System-on-Chips

Claudia Tempesta

Implementation and evaluation of a Real-Time Multi-core Scheduler for Automotive System-on-Chips.

Rel. Paolo Bernardi. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2022

Abstract:

Implementation and evaluation of a Real-Time Multi-core Scheduler for Automotive System-on-Chips Chip manufacturers are starting to introduce several computational units (CPUs), integrated into the same System-on-Chip (SoC), to boost performance. It is therefore necessary a Multi-core Operating System able to manage the cores’ synchronization and multiple accesses to shared resources respecting time constraints and deterministic behavior. The scheduler proposed in this thesis is based on a Symmetric Multi-Processing, it has a single image of the RTOS shared by many cores, so each core can run the scheduler and access the shared memory executing tasks independently from the other cores. The scheduling approach is Global scheduling using a shared task ready queue. All cores’ personal variables like pointers to the currently executing task or its priority, necessary in the scheduler and in the main Operating System’s functions to follow tasks execution, are vectorized and indexed by the Processor ID. In this way, each core can run the Scheduler and handle its tasks with complete independence. To manage properly the shared ready queue we propose an algorithm able to avoid that more than cores execute the same task assigning to each core running the scheduler the first available task with the highest priority. Due to shared scheduler and resources, particular attention is required on synchronization and data coherency. In the proposed approach all the accesses to main shared variables, such as the ready queue, are protected by a lock. The case of study of this thesis is a real automotive SoC, ST Microelectronics SPC58 family. It has a multi-core architecture composed of three cores, with private memories and caches, and shared memory resources and peripherals. As a software starting point, it is used RTOS Micrium C-OS III in a single-core version modified and scaled into the multi-core explained approach.

Relators: Paolo Bernardi
Academic year: 2021/22
Publication type: Electronic
Number of Pages: 74
Additional Information: Tesi secretata. Fulltext non presente
Subjects:
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Ente in cotutela: Ecole Centrale (FRANCIA)
Aziende collaboratrici: UNSPECIFIED
URI: http://webthesis.biblio.polito.it/id/eprint/22692
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