Politecnico di Torino (logo)

DFT and Testability Strategy for an Analog On Top System On Chip for Mobile Communication Applications

Thomas Gurgone

DFT and Testability Strategy for an Analog On Top System On Chip for Mobile Communication Applications.

Rel. Maurizio Martina. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2021


During the development of an IC, from the very first project steps, is fundamental to identify the testing strategy. In fact, modern process technologies and design tools allow the realization of really complex chip in which are present million of transistors and the possibility that one of them doesn't work correctly is very high. Before selling a chip, it is necessary to test it, in order to be sure that the IC is working properly. The manufacturing tests are performed in order to guarantee the correct behavior of the IC. Increasing the complexity of the ICs, also means increasing the time needed for the manufacturing tests. This causes an increase in time to market. For all these reasons, techniques which allow the debug and testing in faster way are necessary: The Design For Testability (DFT) techniques becomes fundamental during the design flow. This thesis investigates the DFT techniques applicable in an IC in order to increase the testability. The aim of this thesis is: to identify and to explain the most used Design For Testability techniques adopted during the design flow, to talk about how DFT techniques are implemented during the chip development at the STMicroelectronics and to talk about the results obtained. The aim of this project is to show how the use of DFT techniques introduce means to reduce and facilitate manufacturing tests, reducing also the time needed to validate an IC. In addition, the aim of the thesis is also to show how DFT techniques are fundamental for diagnostics, ensuring greater observability and controllability of IC.

Relators: Maurizio Martina
Academic year: 2021/22
Publication type: Electronic
Number of Pages: 109
Additional Information: Tesi secretata. Fulltext non presente
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: STMicroelectronics
URI: http://webthesis.biblio.polito.it/id/eprint/21270
Modify record (reserved for operators) Modify record (reserved for operators)