library ieee;
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all; 

entity Reg1 is
port
(
	CLK:	in	 std_logic;
	Rst_n:	in	 std_logic;
	En:		in	 std_logic;
	Clr:    in   std_logic := '0';
	D:		in	 std_logic;
	Q:		out std_logic
);
end Reg1;

architecture Reg1Imp of Reg1 is

begin
	
RegProc: process (CLK, Rst_n, Clr, En) is
begin
    if Rst_n = '0' then
        Q <= '0';
	elsif rising_edge(CLK) then				
		
		if Clr='1' then
		  Q <= '0';
		elsif EN = '1' then
			Q <= D;
		end if;
	end if;
end process;

end Reg1Imp;


