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Design Technology Co-Optimization Techniques for enabling energy-efficient Analog In-Memory Computing hardware using IGZO technology

Nazareno Sacchi

Design Technology Co-Optimization Techniques for enabling energy-efficient Analog In-Memory Computing hardware using IGZO technology.

Rel. Gianluca Piccinini, William Fornaciari. Politecnico di Torino, Corso di laurea magistrale in Nanotechnologies For Icts (Nanotecnologie Per Le Ict), 2021

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Due to an increasing global interest towards sustainable and intelligent nano-chips and the need to sense the world at the extreme edge, a shift in microprocessor design is requested, since Von-Neumann architectures does not give considerable gain in term of speed and energy anymore. Considering also the end of the scaling era, disruptive approaches are needed in order to make systems which are power efficient and interacts with the world. Interaction has been empowered by use of Deep Learning, a paradigm of Artificial Intelligence (A.I.) in which an algorithm is trained by data in order to make inference, that is make rules and discover patterns. Algorithms with this function are mainly composed of affine transformations, that consist in matrix-vector multiplication (MVM) with several multiply-accumulate operation (MAC) which constitutes the main bottleneck of Deep Learning in terms of energy and delay. MVM is an operation that can be easily performed in a parallel architecture, which speed up the operation and avoid interconnects bottleneck if performed in memory. Moreover, Deep learning accuracy constraint does not require full precision, making analog computation possible. Henceforth, an alternative solution to Von-Neumann Architecture for Deep learning in the extreme edge is Analog in-Memory Computing (AiMC). The approach adopted consists in a crossbar where weights are stored in memory cells. Digital data inputs are converted in the analog domain to make the computation and the analog result is converted back in digital. This structure can be obtained with several combinations of technologies and topologies, requiring a wide design-space research. First of all, the memory cell technologies has to be set. IGZO, SOT-MRAM and SRAM are compared, adopting the first option, preferable in inference. Then, analog temporal encoding has been chosen for input activation encoding and a current-domain computation is set as analog computation, converted in the digital domain by SAR-ADC, chosen due to its low power consumption and the low constraint in sampling frequency. After the elements of the crossbar have been set, they have to be gathered such that the system operate correctly. The memory-cell where the computation occurs have been modeled as a linear element in Verilog-A in Cadence Virtuoso and in Python. Then, all the compute cells have been put together considering wire parasitics and Modified Nodal Analysis (MNA) has been adopted with Trapezoidal Rule resolution to obtain the desirable number of cells in a column in the crossbar, the temporal encoding for the computation and the precharge time to perform a MVM operation. Then, the array line with the DAC and ADC have been implemented in Cadence to test its functionality and modify the data-converters already made for ANIA, another DNN accelerator made in IMEC. In the end, a 512x512 crossbar implemented with IGZO technology has been designed, obtaining a theoretical efficiency of 1146 TOPS/W. Timing results have shown a bottleneck, thus other techniques can be explored other than analog temporal encoding, requiring further design-space research.

Relators: Gianluca Piccinini, William Fornaciari
Academic year: 2021/22
Publication type: Electronic
Number of Pages: 120
Corso di laurea: Corso di laurea magistrale in Nanotechnologies For Icts (Nanotecnologie Per Le Ict)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Ente in cotutela: Nonprofit company (BELGIO)
Aziende collaboratrici: IMEC
URI: http://webthesis.biblio.polito.it/id/eprint/20394
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