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BEOL CMOS-Compatible Ferroelectric Fin-FET for Neuromorphic computing.

Donato Francesco Falcone

BEOL CMOS-Compatible Ferroelectric Fin-FET for Neuromorphic computing.

Rel. Carlo Ricciardi. Politecnico di Torino, Corso di laurea magistrale in Nanotechnologies For Icts (Nanotecnologie Per Le Ict), 2021

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The way in which hardware components are organized into a functional computer, namely the von Neumann architecture, has barely changed since its inception in 1945. The bottleneck of this architecture consists in the huge data transferring between the processor and the memory. Nevertheless, with the advent of the Internet of Things (IOT) and the Artificial Intelligence (AI), an exponential growth in the amount of processed data, has imposed critical requirements in terms of energy efficiency and processing speed. Neuromorphic hardware allows to perform computing at the site where data is stored, offering an attractive solution for these issues. Neuromorphic architecture can be based on a memristor, known as a programmable resistor, which is a circuit element that changes its resistance depending on how much charge flowed through it. Ferroelectric based memristors are a promising candidate to build energy efficient neuromorphic hardware. In this work, a ferroelectric Hf0.57-Zr0.43-O2 (HZO) field-effect transistor (FeFET) memristor has been electrically characterized in order to study the conduction mechanisms, as well as the physics behind the resistive switching, governed by the polarization screening charge in a WOx channel. In particular, to find out the conduction nature both along the channel and through the gate stack, temperature-dependent electrical measurements have been carried out. In addition to the physical understanding of FeFET devices, to overcome the performance of standard planar devices, a new generation of devices has been processed and characterized, the Fin-FeFETs. They allow to increase the electrostatic gate control of the channel, and thereby getting a better resistive switching. The whole process flow has been studied and optimized, to achieve a fin's resolution of less than 10nm width. These devices can be used in cross-bar array configuration to allow energy efficient vector-matrix multiplication, as well as Hebbian learning and Spike-timing dependent plasticity (STDP) for spiking neural network tasks.

Relators: Carlo Ricciardi
Academic year: 2021/22
Publication type: Electronic
Number of Pages: 90
Corso di laurea: Corso di laurea magistrale in Nanotechnologies For Icts (Nanotecnologie Per Le Ict)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Ente in cotutela: IBM Zürich Research Lab (SVIZZERA)
Aziende collaboratrici: IBM Research GmbH
URI: http://webthesis.biblio.polito.it/id/eprint/20379
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