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Development of a multi-kernel RTOS for RISC-V embedded SoC.

Fabio Baldo

Development of a multi-kernel RTOS for RISC-V embedded SoC.

Rel. Maurizio Zamboni, Giovanna Turvani. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2021

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Multi-core architectures, thanks to their exceptional power efficiency and performance, are becoming widely used in embedded system products. This changing trend has pushed all developers to adapt their programs to take advantage of the new possibilities, coming from the use of multi-core devices. When this restructuring process is applied to Real Time Operating Systems, multiple and different approaches can be followed. This thesis aims, firstly, at analysing the main possible solutions for porting the single-core version of the RTOS u111, made by CSEM SA, to a multi-core SoC, based on a RISC-V 64-bits architecture. It then illustrates the whole process behind the final adaptation of the single-core version of the RTOS to a multi-kernel structure based on a shared memory configuration. Eventually, it describes the development process of an Inter Kernel Communication system, designed to be compatible with most of the multi-core embedded SoCs, from the initial design of the protocol to the final implementation of a dedicated API, which have been eventually tested using the Kendryte K210 SoC in the MaixDuino board.

Relators: Maurizio Zamboni, Giovanna Turvani
Academic year: 2020/21
Publication type: Electronic
Number of Pages: 124
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: Haute école d'ingénierie et d'architecture de Fribourg
URI: http://webthesis.biblio.polito.it/id/eprint/19224
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