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FPGA qualification for the LHC radiation environment

Antonio Scialdone

FPGA qualification for the LHC radiation environment.

Rel. Luca Sterpone. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2021

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At CERN, many electronic systems need to operate in a radiation environment along with the Large Hadron Collider (LHC). Thus, the Radiation Hardness Assurance (RHA) of electronic components is fundamental to ensure the reliable functioning of accelerators and experiments. Because of their benefits in terms of costs, flexibility, and performances, Field Programmable Gate Arrays (FPGAs) are often the core of several electronic systems. However, their lifetime and performances are affected by radiation-induced effects such as Single-Event Effects (SEE) and Total Ionizing Dose (TID). This creates the necessity to perform many qualification tests to find a suitable FPGA to use in a specific system or experiment. Moreover, the upcoming upgrade of the LHC, the High-Luminosity LHC (HL-LHC), will bring many improvements to the present experiment, but radiation levels will increase. Therefore, more robust FPGAs are necessary, making the qualification process even more important. The current qualification procedure consists of testing the FPGA’s internal components individually, retrieving a general overview of the FPGA sensitivity to radiations. Then, the specific application is tested to estimate the failure rate of the device when working inside the LHC. This procedure implies performing a radiation test for each application we want to run, which is time-consuming and very expensive. In this work, we present a new approach based on benchmark circuits that solves this problematic. These benchmark circuits reflect the workload of an actual application, allowing to perform standardized application-level testing that facilitates the comparison of results between different FPGAs and different experiments. Most importantly, the procedure allows us to estimate the device failure rate independently from the application we plan to use, thus reducing the number of radiation tests we need to perform. The benchmark application we used belongs to the ITC99 Benchmark suite developed in the CAD group at Politecnico di Torino. In addition, we developed an FPGA-based tester architecture to carry out radiation tests. The tester platform is based on an SoC, with an embedded processor connected to an FPGA. We developed Intellectual Property (IP) cores in VHDL implementing the different test routines to test the FPGA under radiation, and we developed the high-level APIs for the embedded processor to communicate with such IPs. With this approach, we greatly simplified the entire radiation process. Using this platform, we performed various radiation campaigns against protons and neutrons, qualifying two FPGAs for the CERN applications: the NG-Medium (SRAM-based) and the PolarFire (FLASH-based). We demonstrated how, we can easily compare the two FPGAs, even if they are based on two different technologies, and we estimated their failure rate for twelve years of operations inside the HL-LHC.

Relators: Luca Sterpone
Academic year: 2020/21
Publication type: Electronic
Number of Pages: 82
Corso di laurea: Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering)
Classe di laurea: New organization > Master science > LM-32 - COMPUTER SYSTEMS ENGINEERING
Aziende collaboratrici: CERN
URI: http://webthesis.biblio.polito.it/id/eprint/19117
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