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Artificial neural networks in hardware: design of a multi-device measurement setup for advanced parallel neuromorphic computation

Michelangelo Barocci

Artificial neural networks in hardware: design of a multi-device measurement setup for advanced parallel neuromorphic computation.

Rel. Danilo Demarchi. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2021


The popularity of data has exponentially grown in the last decade, to such a level that it has been defined "the world’s most valuable resource" (The Economist, May 16th 2017). This led many universities and researchers to divert their focus into what is called now data science, where machine learning algorithms are exploited to study data in order to make predictions or classifications. While the concept of neural networks may be considered widely spread, i.e. making predictions and learning from input datasets using fictitious structures that emulate the human brain, there are other approaches that are taken towards exploiting machine learning techniques in a faster, more power-efficient way. Such efficiency can be achieved for example by implementing neural networks in hardware, where inputs and outputs (e.g. feature vectors and classes, respectively) are represented and encoded by voltages and currents. Many efforts are being pursued in this direction: an example is given by researchers at ICSC Institute of Microelectronics of Beijing, who were capable of implementing a convolutional neural network trained to classify handwritten digits fully in hardware using memristive technology. Another significant breakthrough was achieved by researchers at University of Twente’s BRAINS center for neuromorphic computing, who developed boron doped silicon chips that exploit nanoelectronic properties of semiconductors to obtain neuromorphic features. The phenomenon is called hopping conduction, and thanks to that the material shows tunable, non-linear behaviour: these features made it possible to successfully perform classification tasks like boolean logic gates and handwritten digit recognition by properly tuning the voltages on the chips’ input electrodes, similarly to what is done with traditional artificial neural networks parameters optimization in deep learning applications. The capability of handling multiple chips at the same time is a necessary improvement both at the early stages of the research, when a faster validation process, hence a higher throughput, is required as the functionality of devices is tested to see if the fabrication process went as expected, and at the actual experimentation stage, when more structured and interconnected architectures have to be created in order to perform more complicated tasks and predictions: the work depicted here aims to provide a feasible solution to these new requirements by extracting the needed technical specifications and describing the design process of the new measurement setup for the BRAINS research center, including the hardware choice, the PCBs design and validation, and the Python code development.

Relators: Danilo Demarchi
Academic year: 2020/21
Publication type: Electronic
Number of Pages: 61
Additional Information: Tesi secretata. Fulltext non presente
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: University of Twente
URI: http://webthesis.biblio.polito.it/id/eprint/17921
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