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Design and Modelling of Magnonic Circuits

Huqing Zheng

Design and Modelling of Magnonic Circuits.

Rel. Maurizio Zamboni, Fabrizio Riente, Umberto Garlando. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2021


The Moore’s law predicts that the number of transistors inside integrated circuit doubles every 18 months. This is possible thanks to dimensions scaling of CMOS (complementary metal oxide semiconductor) technology. However, the scaling process has physical limitations. The power density increases dramatically with the dimensions scaling and the performance of circuit, that is the main issue. For this reason, a set of new technologies is developed. One possibility is Magnonics. This technology exploits the propagation of Spin-waves inside waveguides realized with Yttrium ion Garnet. When two identical waveguides are placed sufficiently close to each other, their dipolar interaction causes a splitting of the dispersion curve into the symmetric mode and the antisymmetric mode. With a certain spin-wave frequency, it is possible to excite both the modes propagation. The interaction between two modes leads to a periodic energy transfer between two waveguides. This is the key idea of operational principle of magnonic circuits. In the first part of the thesis, Magnonics theory and an example of magnonic half-adder (developed from university of Vienna) are introduced. The goal of the second part of the thesis is to create the MATLAB models of magnonic building blocks for simulation purposes. The basic idea is to have a flexible simulation environment that allows to simulate different circuits. It is verified that the outputs of magnonic half-adder can not be directly used as inputs of the next gate. The uncertainties of the outputs (degraded logic values) cause an error in the next gate. One solution to this interface problem between two logic gates consists of regenerating the output waves to reach a high accuracy. To do this, two new regenerator blocks are designed. In this way, the two regenerators are inserted in the half-adder outputs. This new structure is the basic component to implement other logic gates and complex circuits. Possible implementations of NOT and OR gates using a basic half-adder are proposed. They allow the building of complex circuits, in particular complex adders. In this thesis, the generalized N-bit Ripple-Carry adder (RCA) and Carry-Skip adder (CSA) are implemented and simulated. In order to simplify the simulation, a dedicated Test-bench is developed. The simulation results of 32-bit RCA and 48-bit CSA show that the outputs have a good separation between logic ‘1’ and logic ‘0’ thanks to the regenerators. In conclusion, the simulation results demonstrate that a magnonic logic gate can be directly connected to another one if its outputs are accurate. To do this, regenerator blocks are required in magnonic circuits.

Relators: Maurizio Zamboni, Fabrizio Riente, Umberto Garlando
Academic year: 2020/21
Publication type: Electronic
Number of Pages: 169
Additional Information: Tesi secretata. Fulltext non presente
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: UNSPECIFIED
URI: http://webthesis.biblio.polito.it/id/eprint/17857
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