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High-Level Synthesis for Ultralow Power FPGAs

Davide Salusso

High-Level Synthesis for Ultralow Power FPGAs.

Rel. Mihai Teodor Lazarescu. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2020

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The subject of this thesis is the capacitive sensors used in locating people indoors, especially in the health care of the elderly. This sensors have numerous advantages: cost, power, privacy and ease of installation while their main disadvantage is the steep loss of sensitivity by increasing the distance between the sensor and the person. To reduce the cost and installation complexity, the sensors are used in load mode, so only one plate of the capacity is needed because the other plate is the person's body along with the surrounding environment. In this thesis instead of processing the data on board the sensor with a micro-controller we used an ultralow-power FPGA like a hardware accelerator, and to process the data we use a neural network (NN) of the Multi-layer perceptron (MLP) type that have two hidden layers formed by eight neurons each and an output layer formed by a neuron. It takes six 16-bit inputs and generates one output of four-bit. The C code of this NN will be synthesized using Vivado HLS, which also allows to insert directives to optimize the generated code, and they have been added in such a way as to being able to explore multiple solutions, starting from a low level of parallelism and then increasing it from solution to solution. After that, through a Co-simulation, again on Vivado HLS, it was verified that the synthesized code still worked as expected. Then the created VDHL code will be compiled using the ultralow-power FPGA tools, which are: Radiant for ICE40UP5K of the Lattice iCE40 family and Libero for AGLN250, M1AGL600 and M1AGL1000 of the Microsemi IGLOO family. We will then compare the results obtained in terms of inference time, energy, power, clock frequency, clock cycles and area, to the data obtained in another experiment where the NN was written manually. Many solutions have been created for the different FPGAs, and there are different implementations of the same solution as we tried to change the clock period imposed on HLS and see what effect it would have on the final implementation. The main problems of the implemented solutions is that the more directives were inserted, the more area it was going to occupy, and this was not controllable because Vivado HLS synthesizes the C code according to the own logic, so maybe it inserts elements that in reality could be omitted. The other problem is that the code generated by HLS should be implemented on FPGAs of the Xilinx family, but instead is implemented on ultralow-power FPGAs, that are of a different families from Xilinx, so there may be a problem of compatibility. The results of the manual programming of the NN achieved by the reference model were not achieved for all the FPGAs, in particular for the AGLN250 and the M1AGL600 (even if in any case the values of the data found are not far from the target ones). While with the Lattice FPGA the lowest power and energy (5.23 mW and 5.78 nJ) of both HLS and manual programming implementation are obtained, this because the multiplication that are the operations that require more resources are assigned to the DSPs thus not consuming any other area and thus allowing to add directives to obtain maximum parallelism. Also the inference time find is good 1.10 us. With the Microsemi M1AGL1000 FPGA, the largest, it was possible to achieve excellent results, in particular the lowest inference time (0.86 us) among all FPGAs with HLS implementation was obtained and also a good energy (17.27nJ).

Relators: Mihai Teodor Lazarescu
Academic year: 2020/21
Publication type: Electronic
Number of Pages: 111
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: UNSPECIFIED
URI: http://webthesis.biblio.polito.it/id/eprint/16047
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