Politecnico di Torino (logo)

Spiking Neural Hardware Emulator based on Zynq PSoC

Roberto Gattuso

Spiking Neural Hardware Emulator based on Zynq PSoC.

Rel. Maurizio Martina. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2020

[img] PDF (Tesi_di_laurea) - Tesi
Restricted to: Repository staff only until 26 September 2021 (embargo date).
Licenza: Creative Commons Attribution Non-commercial No Derivatives.

Download (3MB)

This thesis work is focussed on the scalability and virtualization enhancement of HEENS architecture, which is a spiking neural hardware emulator. All blocks are described in VHDL, simulated to check their behaviour and finally the whole system is synthesized and implemented on a PSOC, in order to verify time constraints and area occupied. In particular, all the improvements concern the processing element array, which represents spiking neurons that have to be emulated. Each processing element consists of an ALU, a register file, a virtualization register, a LFSR and memory blocks containing synaptic parameters and membrane potential values. Finally the architecture has a new spike distribution structure, making the system more scalable, and virtualization is introduced, in order to extend the array without requiring more hardware resources, thus saving space on the board. Exploiting at most the available area, it has been possible to simulate a 13x13 array with problem-free timings.

Relators: Maurizio Martina
Academic year: 2019/20
Publication type: Electronic
Number of Pages: 103
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: UNSPECIFIED
URI: http://webthesis.biblio.polito.it/id/eprint/14380
Modify record (reserved for operators) Modify record (reserved for operators)