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UVM Test-bench acceleration on FPGA

Giulia Cioffi

UVM Test-bench acceleration on FPGA.

Rel. Edgar Ernesto Sanchez Sanchez. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2020

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The complexity of intergated circuits is increasing much faster than what CAD tools can handle. Even at IP level test cases can run for several hours or even days. Researchers and developers have introduced several techniques to tackle this issue. One promising ap- proach to speed-up the veri cation process is co-emulation. Before diving into details, this thesis gives a background on Universal Veri cation Method- ology (UVM) which allows Test-bench modularity and reusability. The available co- emulation techniques and their advantages and drawbacks are then discussed, with par- ticular focus on the one used in this research project: Test-bench acceleration. The rst part of the thesis concludes with the state of the art of existing Test-bench accelera- tion implementations and the evaluation of common weaknesses. The core of the thesis focuses on the description of the developed architecture and the adopted case study: a period jitter monitor. The SW Test-bench has been written in Python according to UVM. This allows to execute it from any workstation on which Python is installed. SW-HW communication is performed using Accellera's Standard Co-Emulation Modeling Interface (SCE-MI). While the available versions of the standard are written in C/C++, for this project a Python version of it has been de ned and used. The platform used to perform hardware acceleration has been Arria 10 FPGA. To evaluate the performance of the de- signed infrastructure, the same test scenarios have been executed both in RTL simulation and Test-bench acceleration and the execution times have been compared. For 1 million of jitter measurements, RTL simulation requires several days. The same test case, executed with Test-bench acceleration on FPGA, completes in few minutes. The speed-up factors obtained with the developed co-emulation infrastructure are between 750x and 2000x. This thesis conlcudes with some suggestions on how to additionally improve the infras- tructure performance and speed-up the SW-HW communication.

Relators: Edgar Ernesto Sanchez Sanchez
Academic year: 2019/20
Publication type: Electronic
Number of Pages: 89
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Ente in cotutela: KTH - Kungl. Tekniska Hogskolan (Royal Institute of Technology) (SVEZIA)
Aziende collaboratrici: UNSPECIFIED
URI: http://webthesis.biblio.polito.it/id/eprint/14361
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