The present work discusses a framework for improving System Level testability of an Automotive SoC exploiting the Evolutionary Optimizer microGP to maximize core switching activity. The present framework is meant for DUTs operating at voltages under specification, in order to exacerbate latent delay faults. The optimizer, provided with a set of instructions and operands, evolves generations of candidate Assembly programs. Each program is then simulated and ranked to progressively increase the switching activity. Moreover, the ranking algorithm exploits a graph-based representation of instructions to penalize individuals with a high percentage of Write-After-Write hazards, which prevent the detection of errors occurred during the execution of the test program.