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ADC noise measurement on FPGA board

Luca Fonticelli

ADC noise measurement on FPGA board.

Rel. Giovanni Antonio Costanzo. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2019

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Improvements in electronic have allowed front-end part in communication systems to be faster and more precise: the focus on this part of a device is justified as the communication with the external world has to keep the rhythm with the high speed calculations of every CPU. Every application requires then a reliable and low noise-conditioned devices able to reach performances we use every day. New techniques are developing also in time - frequency metrology field, where the low noise rate is required to achieve high measurement accuracy. The use of new SoC commercial boards, composed by a programmable logic and processing system, is a matter of interest in this field in order to develop new measurement flows: this kind of applications are reliable in terms of flexibility, where on-the-fly test and re-programming hardware are required, and quite fast in processing data thanks to last years' CPU presence. Implementing board-style techniques could allow researchers to avoid complex instruments tune and long measurement chain in favor of a deep versatility. However, this kind of adaptability may be limited by main blocks inside every commercial board: ADC and DAC for front-end, clock generation (i.e. PLL), distribution and interconnections for back-end. In this context, my thesis work is focused on analyzing and selecting the main noise figures of merit of the Analog to Digital converter, principal block of the front-end, selecting testing techniques and finding a way to implement them using this board potential. Two hardware projects have been designed and implemented using VHDL language and loaded on FPGA part of the System on a Chip. Data have been generated with Agilent instruments, directly processed and converted in the Programmable Logic part and packetized and sent by the Processing System to the main computer: here data have been processed and analyzed using Matlab and many figures and values have been computed and here presented and commented, to understand which could be the frequency performances limiting factor and whether these boundaries could be corrected or not. The figures of merit here presented can be used to analyze other front end part, proposing a complete overview of commercial boards' limiting factor. At the end some improvements are speculated and presented for further developments: these techniques could also be modified to make the board analyze them directly, and other modifications could be designed to increase test flow speed. This project is a part of a bigger and more complex Red Pitaya characterization carried on at INRiM by Dr. Cardenas and Dr. Calosso, to develop a deep knowledge of this architecture: this can lead to an implementation of this kind of boards in high-specialised techniques, as fiber dissemination and reception of signals to synchronize different research laboratories.

Relators: Giovanni Antonio Costanzo
Academic year: 2019/20
Publication type: Electronic
Number of Pages: 74
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: New organization > Master science > LM-29 - ELECTRONIC ENGINEERING
Aziende collaboratrici: INRIM Ist.Nazionale Ricerca Metrologica
URI: http://webthesis.biblio.polito.it/id/eprint/12535
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