Paolo Monti
Optimization techniques for address translation caches.
Rel. Matteo Sonza Reorda, Edgar Ernesto Sanchez Sanchez. Politecnico di Torino, Master of science program in Computer Engineering, 2019
Abstract
Most modern microprocessor architectures use virtual memory as an abstraction of physical memory to make programs position independent and isolated from each other. While effective, this technique brings a lot of execution overhead, since each memory access needs to be handled by a series of memory lookups, that are by themselves quite slow already. For this reason, a cache-like structure called Translation Lookaside Buffer (TLB) is employed to accelerate virtual-to-physical address translation. It is well known that TLBs have a big impact on system performance, and a great amount of research has already been performed in order to optimize their effectiveness.
This work starts by presenting various techniques already proposed in literature
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