Empirical Approaches: Investigating Solutions to Memory Skewing through Varied Methodologies

Memories are macros with many pins and paths, so they play a critical role in static timing analysis. Due to their numerous and short paths, they are prone to a significant number of hold time violations in specific scenarios with high-voltage. Since even Concurrent Clock and Data (CCD) Optimization technology offered by PNR tools have poor results in solving this problem, this work explores new systematic approaches based on useful skew technique. Useful skew in physical design refers to a deliberate introduction of controlled delay imbalances among clock signals in integrated circuits. This technique helps to improve the timing and performance of high-speed digital design. The proposed solution is starts by analyzing a completed Clock Tree Synthesis of the Hard Macro proposed by the PNR tool. Based on the obtained data, an algorithm capable of finding an optimal negative skew value for each memory is used. Due to feasibility reasons, memories are clustered in groups counting backwards the number of buffers placed by the tool close to them. Different numbers of buffers can be considered for the clustering in order to find a sweet spot for the case under study. Creating memory clusters and apply a specific negative skew for each of them results in less Total Negative Skew (TNS) and Number of Failing Endpoints (NFE) for hold high-voltage scenarios then CCD or applying an arbitrary skew value to all memories.