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DFT optimization able to exploit functional flops to implement test points

Lorenzo Mastrorosa

DFT optimization able to exploit functional flops to implement test points.

Rel. Paolo Bernardi. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2023

Abstract:

The influence digital circuits produced in our society during recent years has increased incredibly. Currently they play a key role in many fields of our everyday life, especially into safety critical systems. These systems have the properties to really threaten the environment and the human life if they don’t behave properly: examples can be found in the automotive and aerospace domains. This is the reason why they must be compliant with strict protocols aiming to ensure really low probabilities of anomalies leading to catastrophic consequences. These protocols are based on several factors among which testing, that must be performed heavily and often, and whose coverage must reach extremely high percentages. In order to implement testing procedures which are able to reach these percentages new techniques were introduced: one of them is test points insertion. This technique is mainly based on the insertion of additional flip flops into the design. These memory elements are not needed by any functional requirements but they are used for testing purposes exclusively. Therefore, despite the increment of dependability, test points insertion causes a not negligible growth on the complexity of the design and this is mainly mirrored in the increase of the testing area overhead. Subsequently, the increment of area leads to an unavoidable growth of the recurrent costs. That’s the reason why companies try to reduce as much as possible this overhead without affecting the overall dependability of the systems. The main objective of the thesis is to implement a theoretical achievement able to reduce the total testing area overhead related to test points insertion without affecting the coverage and to introduce other similar approaches in order to further improve this optimization. The implementation has been carried out with the tools used by the DFT team of Infineon Technologies and the new techniques have been tested on a project under development in the field of automotive microcontrollers.

Relators: Paolo Bernardi
Academic year: 2023/24
Publication type: Electronic
Number of Pages: 84
Additional Information: Tesi secretata. Fulltext non presente
Subjects:
Corso di laurea: Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering)
Classe di laurea: New organization > Master science > LM-32 - COMPUTER SYSTEMS ENGINEERING
Aziende collaboratrici: Infineon Technologies AG
URI: http://webthesis.biblio.polito.it/id/eprint/28516
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