ASIP Design for Motion Estimation in Video Compression Algorithms

Motion Estimation is one of the most complex and time consuming functions of any video compression algorithm. This thesis proposes an ASIP processor, called 'mecore', optimized for Motion Estimation applications. Three versions of the ASIP are realized, starting from the existing 'tmicro' processor model, found in the ASIP Designer software library. Each version provides an increase in performance with respect to the previous one. The first version introduces new instructions, used to support single byte load and store operations, not supported by the original architecture of 'tmicro'. In the second version, two special purpose instructions are added to the 'mecore' instruction set to exploit a new scalar accelerator, designed to speed up the execution of the Sum of Absolute Differences (SAD), that is the most expensive function of the Motion Estimation. The third version extends the 'mecore' instruction set with new Single Instruction Multiple Data (SIMD) instructions, supported by new SIMD hardware accelerators that allow to reach very high performance. The code used for testing the processor computes the Motion Vector of a single Macro Block of size 16x16 pixels over a Search Window of 48x48 pixels, and is executed in only 9.46 us by the last version of 'mecore'. Each version is finally synthesized, using a 65 nm library of cells, exploiting Synopsys Design Compiler.