FPGA-Based Framework for Hardware Acceleration of the HEVC Encoder

HEVC (High Efficiency Video Coding), the most recent standard for video compression, led to an huge increase of the encoding efficiency with the respect to the previous standards but, on the other hand, several tasks became highly time demanding and power consuming. This thesis proposes a fast, dynamically reconfigurable and flexible hardware accelerator for the SATD (Sum of Absolute Transformed Differences), that is one of the cost functions adopted by HM HEVC reference software.The developed hardware block follows all the specification given by HEVC and can work with every Transform Unit size from 8x8 up to 64x64.The accelerator is fast thanks to a highly parallelized architecture. It exploits a datapath subdivided into 4 pipeline stages for the time optimization for the different SATD sizes.This architecture was compiled and adapted in order to work on an FPGA system called DE1-SoC by Intel Altera. On this board is present a Cyclone V chip, that internally includes an ARM processor and, through its buses, the architecture was interfaced with it .Using the microSD interface it was possible to run a Linux distribution and the usage of the FPGA peripheral was integrated in the HM reference software.After that, two main optimizations were introduced. The first one was the clock gating, in order to reduce the power consumption, and the other one was the utilization of the DMA inside the HPS, to increase the throughput of the data from the processor memories to the FPGA.At the end, the adders present in the datapath were substituted with Error Tolerant Adders, with the aim of analyzing the effects of approximation on the Rate Distortion.