Development of a programmable hardware command in the context of high speed serial links

In the era of technological innovation and increasing performance demands, input/output (I/O) systems play a significant role in data exchange between the components of electronic systems. Applications such as artificial intelligence, 5G networks, high-performance computing (HPC), and advanced automotive systems (ADAS) require faster and more efficient solutions for transmitting and receiving large amounts of data. In this context, high-speed SerDes (High-Speed Serializer/Deserializer) systems have become a key technology, they currently represent the predominant implementation of I/O interfaces capable of supporting data transmission rates exceeding 100 Gbps. A SerDes system is mainly composed of two functional blocks: the transmitter and the receiver. The transmitter converts parallel data into a high-speed serial stream, whereas the receiver deserializes the incoming stream to restore the original parallel format. The SerDes includes a Physical Medium Dependent (PMD) section, responsible for the overall control of the components through multiple finite state machines (FSMs). It manages power-up and power-down requests, rate change operations, provides the interface with the firmware and performs limited data conditioning functions. The focus of this project, in collaboration with Synopsys, is on the power-state management within the PMD. There is a Look-Up Table (LUT) storing the instructions and configuration data required to handle power state transitions efficiently. Nowadays each command is mapped to a specific signal, that is conditioned by some FSMs. This approach is highly rigid, as any modification of a command requires rewriting the hardware description or, in the worst case, re-fabricating the silicon. The main goal is having a programmable hardware command in order to have more flexibility. Firstly, a new module was created. It manages both the existing hardware commands and new ones, with the exception of one that has a dedicated FSM. Then the module was instantiated in one of the modules in the PMD that handles the power up/down sequences. The old and the new implementations were simulated to actually check that the behavior was correct and equal. Finally, the synthesis of both has been done in order to be able mainly to compare the differences in area and power.