Solid-State Simulations Advancing Conventional Processes Toward Spin Qubit Technologies

Quantum computers are emerging as a revolutionary technology that exploits qubits, confined in one-dimensional quantum dots, to address complex problems that are currently beyond the reach of classical computers. In this work, a fully automated simulation framework was developed to investigate both the quantum dot confinement and transport behavior of custom designed semiconductor devices as host platforms for spin qubits, and subsequently simulate their fabrication using standard CMOS fabrication processes. The architecture considered is the planar MOS on a SOI wafer substrate, a highly mature design that can be fabricated through well-known processes extensively documented in the literature and remains feasible for manufacturing even for low-volume research laboratories. The solid-state simulations were performed within QTCAD, a quantum technology simulation platform developed by Nanoacademic Technologies Inc. The geometries for each device are modelled in Fusion, a CAD software from Autodesk, in this work used under a personal non-commercial licence. It allows the extrusion of solid geometries from parametrically drawn two-dimensional sketches, enabling the use of variables that automatically update the entire geometry upon modification, thus enabling fast and accurate resizing. After verifying the device confinement, the architecture and physical dimensions are transferred to Synopsys Sentaurus Process for fabrication simulations. The results from SProcess can then inform modifications to the original geometry, which is subsequently re-simulated to evaluate quantum behavior and refine fabrication steps in order to achieve optimal performance. To ensure reasonable coherence times, it is necessary to avoid hyperfine interactions arising from the non-zero nuclear spin of the silicon isotope 29Si, naturally present in electronic-grade silicon. This requirement can be fulfilled by growing a 28Si layer with 99.99% isotopic purity on top of a FD-SOI wafer from Soitec through epitaxial growth using enriched silane gas. The results from quantum simulations can be post-processed to generate additional plots and carry out further investigations about the device behaviour. The primary focus was on planar devices fabricated on SOI wafer substrates, but the investigation was also extended for some three-dimensional structures like Fins and Nanowire Gate-All-Around. Seven devices were defined: a planar single quantum dot (SQD) and double quantum dot (DQD), along with two variants incorporating modeled doping profiles (obtained by SProcess doping simulations via thermal diffusion) within the source/drain contacts; a SQD FinFET-like structure; and both SQD and DQD Nanowire GAAFET-like structures. Each device provided clear evidence that the confinement and transport behavior are satisfactory and consistent with expectations, demonstrating that the developed workflow performs as intended and constitutes a practical tool for investigating the suitability of these devices as platforms for hosting spin qubits. In conclusion, the high degree of customizability of this workflow enables solid-state simulations of fully customized complex geometries, while providing extensive options for displaying and post-processing the obtained data. Future work could involve integrating results from Sentaurus Process into the simulation framework. Of particular interest is the consideration of process variations, in order to assess their impact on device behavior and evaluate the robustness of the devices against them.