Rapid Prototyping of Edge AI Accelerators: An HLS-based Approach for CNNs on FPGAs for the AIdge ML Deployment Framework

The computational demands of modern Artificial Intelligence (AI), particularly for Convolutional Neural Networks (CNNs) in computer vision, are increasingly challenging to meet with traditional cloud-centric approaches. Relying solely on centralized cloud infrastructures introduces significant latency and bandwidth bottlenecks, while also raising concerns about data privacy and the substantial energy consumption of large-scale data centers. To overcome these limitations, the paradigm of edge computing has gained prominence, processing data locally on dedicated hardware. This work explores the deployment of CNNs on Field-Programmable Gate Arrays (FPGAs), reconfigurable devices that offer a compelling blend of parallel processing capability and energy efficiency for edge applications. This thesis investigates a rapid prototyping methodology for FPGA-based CNN acceleration, leveraging the High-Level Synthesis (HLS) design flow. The research focuses on the implementation and optimization of critical network layers, including quantization and pooling, to create a library of hardware-efficient functions. By abstracting the low-level hardware complexity through HLS, this work enables a streamlined path from a software-defined model to a customized hardware implementation. The final synthesis and deployment phase aims to validate this prototyping approach, fine-tuning the system for optimal performance on the target FPGA. The primary contribution of this work is a demonstrated methodology that significantly accelerates the development cycle for edge AI accelerators. This approach facilitates rapid exploration of the design space, allowing for quick evaluation of different model architectures and hardware optimization strategies on FPGAs. The findings contribute to making efficient, low-latency AI inference more accessible by reducing the barrier to entry and development time for hardware deployment.