Design of a UVM Based RISC-V model for Digital Functional Verification

The continuous growth in complexity of modern digital systems and the rapid diffusion of the open RISC-V Instruction Set Architecture have made functional verification a fundamental step in the design flow. Ensuring that a processor behaves correctly under all possible operating conditions is increasingly challenging, and verification today often represents the largest share of the overall design effort. For this reason, advanced methodologies such as the Universal Verification Methodology (UVM) are essential to build reliable, reusable, and scalable verification environments. In this thesis, a UVM-based framework was set up to verify a RISC-V processor. The work focuses on the CV32E20 core from the OpenHW Group’s CORE-V family as the main reference and builds an environment that can handle both the base ISA and selected custom extensions. The testbench is organized in layers and brings together different components such as stimulus generators, monitors, scoreboards, and a reference model used to check the execution of instructions. A key aspect of the framework is its extensibility. The environment is designed to connect with the Core-V eXtension Interface (CV-X-IF), allowing the verification not only of the standard pipeline but also of coprocessors and custom ISA instruc- tions. This modular structure makes the framework adaptable to future processor developments and reusable across projects. The results confirm that the UVM-based approach improves the efficiency and reliability of the verification process. The framework helps detect functional issues, check compliance with the RISC-V specification, and validate new features. Overall, this work demonstrates how a structured UVM methodology can support the design of dependable and energy-efficient RISC-V systems.