Fabrication and electrical characterization of ferroelectric Si-doped HfO2 thin films for cryo-electronic memory devices

The discovery of ferroelectricity in the non-centrosymmetric orthorhombic crystal phase of HfO2 in 2011 has led to renewed interest in ferroelectric non-volatile memories. In particular, the recent widespread attention for hafnia thin films can be attributed to their remarkable performance in terms of low power consumption, remnant polarization, memory window, retention, endurance and switching speed, combined with their already well-known compatibility with CMOS technology. Such qualities meet the growing demand for high-speed computation and high-density data storage, paving the way for technologies such as in-memory computing and neuromorphic computing. These technologies can be implemented using FeFETs (ferroelectric field-effect transistors) and FeCAPs (ferroelectric capacitors). This project focuses on the fabrication and electrical characterization of two main types of HfO2-based devices: MFIS gate-stacks and MFM capacitors, where M is the metal electrode, F is Si:HfO2 (ferroelectric silicon-doped hafnia) and I is the SiO2 dielectric layer between F and the p-doped silicon substrate S. In both devices, the hafnia was deposited using ALD (atomic layer deposition) and crystallized through an RTP (rapid thermal process). The first part is dedicated to the extraction of important information from a non-switching MFIS gate, such as flatband voltage, effective work function of metals and interface trap density. The analysis was carried out mainly by means of the measured capacitance-voltage curves, according to the High-Low frequency method. The study was conducted on three thicknesses of the Si:HfO2 layer, keeping fixed the thickness of the SiO2. Also, different gate metals were used. Then, a further design was tested to increase the voltage drop across the hafnia. This was achieved by reducing the thickness of SiO2 with respect to Si:HfO2, thus balancing their capacitances. The second part is devoted to the study of FeCAPs. These capacitors feature a staggered geometry to prevent the breaking of the hafnia while probing/wire bonding. After performing wake-up cycles by means of applied voltage pulses, important figures of merit were extracted, including the remnant polarization 2 Pr, the memory window 2 Vc, the maximum and the baseline capacitance. The measurements were performed at first at room temperature and then at 77 K using liquid nitrogen cooling. The aim was to highlight the impact of a cryogenic environment on the performance of non-volatile memories. The interest for memories working in such harsh environment has in fact grown in the recent years: in quantum computers, for example, qubits operate at temperatures of few mK and the processors must work at maximum 4 K. This has restricted the choice of memories to those able to work at temperatures matching the one of processors, in order to allow low thermal leakage, scalability and high speed. A third part of the thesis focuses on the TCAD Sentaurus simulations of the ion implantation for a correct formation of the source and drain regions of the FeFETs. The type of implantation was a PIII (plasma-immersion ion implantation) and the implanted substrate was an SOI (silicon on insulator). Phosphorous was used as dopant species and different combinations of dose, energy and thermal oxide mask thickness were tested. The aim of these simulations was to verify the presence of a sufficiently high dopant concentration up to few nm from the top silicon surface and to make sure that no penetration of ions occurred inside the BOX.