Migration of register verification methodologies, with focus on workflow automation and profiling

This thesis explores the architectural evolution and verification methodologies associated with modern GPUs, with a particular focus on their role in high-performance and data-intensive applications. General purpose registers are integral to every digital design, thus ensuring reliable read and write functions is crucial. Transitioning from deprecated methodologies, like OVM, to contemporary methodologies, like UVM, aims to enhance efficacy, reduce manual effort, and improve scalability for future designs. The objective is to profile both current and previous methodologies to identify flow limitations and improve the register verification process through automation of design data capture and processing. This migration seeks to eliminate technical debt, ensure scalability, and increase overall efficiency. The main focus is the verification of memory-mapped registers, crucial for hardware-software communication. GPUs serve as the case study due to their complexity and relevance in machine learning and graphics. The methodology explains UVM’s modularity and reusable components, contrasts RGM (limited flexibility) with RAL, which provides an abstract, consistent register model supporting frontdoor and backdoor access. Three strategies are compared: RGM sequencer, RAL frontdoor, and RAL backdoor, using Synopsys VCS for simulation and profiling. Results show RAL backdoor significantly reduces simulation time in frequent polling scenarios, though with slightly higher memory usage. RGM and RAL frontdoor offer better protocol realism but are slower. Introducing delays can improve synchronization. RAL backdoor access is identified as a strong candidate for performance-sensitive verification tasks, especially when protocol overhead can be minimized. Future improvements may include adaptive polling strategies and dynamic access method selection, with potential extensions into power consumption analysis for a more comprehensive evaluation.