Heterogeneous CGRA Cells for FFT acceleration in FMCW radar systems

Efficient and reliable Fast Fourier Transform (FFT) computation is essential for radar signal processing, especially in real-time millimeter-wave (mmWave) Frequency-Modulated Continuous-Wave (FMCW) systems where requirements on throughput, latency, and power consumption are critical. Conventional platforms such as Digital Signal Processors (DSPs), Application-Specific Integrated Circuits (ASICs), and Field-Programmable Gate Arrays (FPGAs) inevitably involve trade- offs, as each technology faces inherent limitations in flexibility, energy efficiency, silicon area, and development complexity. This thesis addresses these challenges by designing a reconfigurable FFT accelerator on the Dynamically Reconfigurable Resource Array (DRRA), a coarse-grained reconfigurable architecture developed by the Silicon Large Grain Objects (SiLago) team at KTH. The proposed design adapts to varying transform sizes and configurations, achieving high throughput and low latency with reduced power consumption. The accelerator is mapped onto the DRRA fabric by instantiating dedicated pro- cessing units, designing efficient memory access schemes, and coordinating the operations through a resource-centric instruction model. The assembly and simulation of the architecture are performed by Vesyla, a domain-specific toolchain for DRRA. Simulation results confirm the functional correctness of the proposed design by direct comparison with the reference model implemented in MATLAB. A further evaluation with a Python-based model shows that the proposed design achieves accuracy levels close to floating-point precision while leveraging fixed-point efficiency, resulting in a relative error of 0.0857% against the reference data and outperforming software implementations using the same numeric format. Synthesis reports indicate that the accelerator, implemented in 22 nm CMOS technology, operates at frequencies up to 1 GHz and achieves a compact silicon footprint of 0.24 mm2. Compared with other memory-based reconfigurable FFT accelerators, this represents a significant reduction in area while maintaining competitive performance. The design also demonstrates strong power efficiency, consuming 98.14 mW and achieving 25.3 nJ per 256-point FFT operation, offering a favorable trade-off between area, throughput, and power consumption. Overall, this work presents a promising solution for next-generation radar systems that combines energy efficiency and flexibility in a compact form factor, suitable for embedded applications. The results demonstrate that the DRRA architecture can deliver high-performance, reconfigurable FFT acceleration, confirming its suitability for demanding signal processing tasks and offering a scalable and reusable framework for future radar and communication systems.