Exploration of High Level Synthesis for the Hardware Design of Digital Signal Processing Systems

The continuously increasing complexity of digital hardware systems has led to a significant rise in design efforts, resulting in high costs in terms of time and resources. In Industry, the need to reduce time-to-market demands for increasing the productivity and requires methodologies capable of shortening development times without compromising the quality of products. In this context, High-Level Synthesis (HLS) emerges as an innovative and strategic solution, raising the level of abstraction in hardware design, overcoming the limitations of traditional manually-written Register Transfer Level (RTL) descriptions and automating hardware generation and verification. HLS translates algorithmic specifications written in high-level languages into optimized RTL descriptions, enabling designers to spend less time dealing with implementation details and to invest resources in algorithm development and system-level optimizations. Nowadays, HLS is mainly applied to algorithm-dependent hardware design, like Digital Signal Processing (DSP) architectures. Catapult from Siemens EDA is an HLS software tool which takes as input an algorithm written in C++ along with a set of user-provided directives and generates an optimized RTL description for a specific target technology. The source code describes the hardware to be developed at a behavioral level, while the directives guide the RTL generation, taking into account technology, I/O interfaces, parallelism, hierarchy, and timing constraints. Since the source code has a high level of abstraction from the hardware, Catapult allows exploring a wide solution space without limitations imposed by hardcoded micro-architectural details, avoiding common errors arising from manual coding of such details. This thesis, related to an internship in STMicroelectronics, focuses on the application of Catapult for the design of complex DSP systems, with a particular focus on automotive applications. The thesis aims to explore the potential of HLS to automate hardware design, evaluating the trade-offs between area, performance, and development time. Starting from the mathematical model of the filters, they are coded in C++, respecting the optimal coding style for HLS. The code is then synthesized using Catapult, and the obtained RTL is verified to ensure full functional correspondence between the software model and the hardware implementation. Two DSP hardware architectures for the automotive industry—one for an airbag safing engine and the other for Electrochemical Impedance Spectroscopy (EIS) processing—were used as benchmarks. Besides ensuring functional hardware, Catapult demonstrated highly competitive area optimization, producing architectures comparable in size to hand-written digital designs. The quality of the C++ code written for synthesis heavily impacts on the quality of the synthesized RTL. Despite the progress made by HLS tools in recent decades, a conscious coding style, taking into account the underlying hardware architecture, the capabilities and the limitations of HLS tools, is essential to achieve optimal implementations. The learning curve is a major obstacle to the adoption of HLS tools; for this reason, the best coding practices learned during the thesis work have been collected in the first chapter and illustrated with code examples and schematics, so that this thesis can also provide designers with practical guidelines for writing C++ code optimized for HLS.