Design of circuital blocks for a for a Low Quiescent Current LDO

The increasing diffusion of portable electronics, biomedical implants and Internet of Things (IoT) devices has intensified the need for integrated circuits capable of operating under stringent energy constraints. In such systems, not only the active power but also the standby power consumption has become a critical factor, as devices often spend the majority of their lifetime in idle or sleep states. Hence, it is crucial to reduce leakage and standby current in order to extend battery lifetime. Today, power consumption is a fundamental constraint that has left a significant footprint in both circuit and system design. A widely adopted solution consists of turning off the Bandgap Generator (BG) of the system by means of a Sample-and- Hold (S/H). In this way, a substantial reduction of the average current consumption can be achieved, provided that the bandgap and the S/H operate correctly. This thesis focuses on the design of specific circuit blocks that enable for the cor- rect operation of a Sampled-based Bandgap Generator with a particular focus on power consumption reduction. To this end a CMOS technique known as LECTOR is adopted to further reduce the dynamic energy consumed by the most critical logic gates. The use of such a configuration in an analog circuit constitutes the novelty and origi- nality of this work. The study is based on an already designed LDO implemented by STmicroelectronics. The goal is to design the local oscillator and the complementary circuitry required to generate the needed control signal for the Bandgap Generator.