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Optimization of Test Architecture in RISC-V Based System-on-Chip

Mauro Lubrini

Optimization of Test Architecture in RISC-V Based System-on-Chip.

Rel. Riccardo Cantoro, Michelangelo Grosso, Iacopo Guglielminetti. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2025

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Abstract:

This thesis optimises test architecture for RISC-V System-on-Chip designs by improving observation coverage for Software-Based Self-Test on the open-source CVA6 processor. As silicon now drives appliances, vehicles, smartphones, and medical devices, robust SoCs and thorough testing are essential. Designs that are easier to test raise yield and shorten time-to-market; periodic online tests executed during normal operation improve reliability and enable at-speed checks. Developed with STMicroelectronics, the work extends an earlier CVA6 study that boosted SBST by inserting observation monitors at random RTL points. Here, randomness is replaced with a principled selection of internal signals whose fault effects are masked and cannot reach primary outputs. Synopsys SpyGlass identifies such locations; although usually applied to place scan elements, its suggestions are repurposed as direct strobe points in functional mode. The study evaluates whether SpyGlass-detected nodes improve coverage over random insertion and over having no added points. Four workflows target the Execution Stage. First, SpyGlass runs at RTL; the design is synthesised; a functional fault simulation then runs while an assembly SBST program exercises the core. Second, after synthesis, SpyGlass analyses the netlist while sequential ATPG patterns are generated; coverage is assessed by comparing Good and Faulty Machines, with elected points routed to extra primary outputs. Third, to isolate point-placement effects, the same ATPG pattern set is reused across SpyGlass, random, and no-point cases. Finally, the Execution Stage is flattened by separating combinational from sequential logic so SpyGlass can assess the combinational portion as a single block; the same simulations are repeated. Results depend on circuit typology. In the purely combinational ALU, SpyGlass-selected points deliver a clear uplift, with coverage rising by up to 6.58% over random selection. In the unmodified Execution Stage, where sequential and combinational logic interleave, the advantage is negligible and coverage trends overlap. When the stage is flattened to expose its combinational core, the improvement reappears: coverage with SpyGlass-guided points is higher by 19,7% than with random points under the same stimulus. This indicates that SpyGlass is effective on combinational regions, while sequentially rich blocks may require additional measures. In conclusion, the thesis validates a method for selecting observation points to enhance SBST on CVA6. It documents flows at RTL and post-synthesis and clarifies where the method has the most impact: in combinational logic or in designs refactored to make that structure explicit. Combining structural analysis with modest refactoring supports higher at-speed, in-field coverage; modules dominated by state may benefit from additional architectural hooks or alternative stimuli.

Relatori: Riccardo Cantoro, Michelangelo Grosso, Iacopo Guglielminetti
Anno accademico: 2025/26
Tipo di pubblicazione: Elettronica
Numero di pagine: 145
Soggetti:
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: Nuovo ordinamento > Laurea magistrale > LM-29 - INGEGNERIA ELETTRONICA
Aziende collaboratrici: STMICROELECTRONICS srl
URI: http://webthesis.biblio.polito.it/id/eprint/37653
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