Model Based Simulation to Support the Decarbonization of Chip Manufacturing

This thesis develops a model based approach to support the decarbonization of a semiconductor assembly line by coupling discrete event simulation with stage level energy and emissions accounting. The case study is a surface mount technology (SMT) line at Hapro Electronics (Line 5, Jaren, Norway). The model, built in AnyLogic, represents PCB assembly flow (preparation, solder paste printing and SPI, pick and place, reflow heating/cooling, AOI, storage) and is parameterized with a mix of sensor readings and equipment data sheets to estimate per stage energy, queueing, throughput, and CO₂ outcomes. Baseline analysis shows a clear separation of levers: the reflow (heating) stage is the dominant energy hotspot and primary driver of the line’s carbon footprint, whereas the pick and place (PnP) station governs flow throughput, cycle time, and work in process (WIP). This insight implies that thermal stability at reflow and congestion management at PnP must be addressed in combination to lower kWh/PCB and kg CO₂/PCB without sacrificing delivery performance. Three main strategies were evaluated. First, batching at the reflow oven (batch size = 7) halves weekly reflow energy (−51.6%, 1,898 → 919 kWh) and reduces total weekly CO₂ by ~40% (26.99 → 16.22 kg) with essentially unchanged weekly throughput; per unit intensity drops from 0.0049 to 0.003 kg/PCB. The trade off is a moderate rise in cycle time at day level due to warm up/standby patterns. Second, alleviating the structural bottleneck by raising effective PnP capacity (10 → 13) collapses the PnP queue and further improves unit carbon intensity (≈0.0030 → 0.0028 kg/PCB) by spreading unavoidable thermal overheads across a larger output. Third, a grid connected on site photovoltaic scenario (69 kWp DC, 100 kVA AC) was sized with PVsyst to supply ~74 MWh in Year 1 (PR ≈ 87%; ~75% of yield in April–September at ~60°N), targeting net 100% coverage of the line’s annual electricity in the first year. Collectively, the results outline a practical roadmap: stabilize the oven’s thermal regime (batching/scheduling), relieve the PnP bottleneck to keep flow smooth, and align the residual electrical load with local low carbon generation. Limitations include a single line scope and partial sub metering granularity; nevertheless, the ordering of levers is robust and suggests a clear path toward a lightweight digital twin that steers feeding and oven occupancy to minimize kWh per PCB under throughput and quality constraints.