
Miriam Quacquarelli
Hardware-Efficient Emulation of Quantum Circuits via Custom Floating-Point Formats.
Rel. Maurizio Zamboni, Giovanna Turvani, Mariagrazia Graziano. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2025
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Abstract: |
This thesis explores the impact of numerical representation on memory usage within a quantum circuit emulator architecture implemented on FPGA. Quantum circuit simulation is memory intensive due to the exponential growth of quantum state space with the number of qubits. Representing an n-qubit system requires storing many complex values—each representing the probability amplitude of a basis state—organized into a quantum state vector. The application of quantum gates involves transformations using unitary matrices of similarly exponential size, making memory efficiency a critical concern in emulation platforms. To reduce memory usage while preserving accuracy, the study explores various numerical representations, including fixed-point, reduced floating-point, and UNUM III (Posit), focusing on values constrained to the interval [-1,+1] which is relevant in quantum emulation as it corresponds to normalized qubit amplitudes. The thesis proposes several reduced-precision formats: three custom floating-point variants and a modified Posit representation. These were specifically designed to improve encoding granularity within the target range. In the case of floating-point formats, exponent bias was adjusted and bit patterns for unused exception codes were reassigned to increase representational density. The custom Posit variant introduces a fixed bias in the regime field to compress values toward zero, emulating exponent bias in floating-point formats. Eight numerical formats were analyzed: two fixed-point, four reduced-precision floating-point and two Posit. MATLAB simulations evaluated their accuracy and encoding efficiency. Two custom floating-point formats emerged as especially promising. These formats were integrated into a quantum emulator architecture based on the method introduced by Conti et al. (2024). Software models were implemented using IEEE-754 32-bit floating-point arithmetic, the current 20-bit fixed-point format, and the two selected custom floating-point formats. The implementations were tested using the mqt-bench benchmarking suite, which includes 145 quantum circuits ranging from 2 to 16 qubits and provides a representative sample of real-world quantum workloads. For the custom formats, multiple combinations of exponent and mantissa widths were explored; the configuration with 16-bit total precision—featuring a 4-bit exponent and an 11-bit mantissa—was identified as the most effective, offering a favorable trade-off between computational efficiency and output fidelity. To assess the quality of the simulation, the state vector produced by each emulator configuration was compared against the reference output generated by Qiskit's state vector simulator. Fidelity, a standard metric for quantifying the similarity between quantum states, was used for evaluation. One of the two custom reduced-precision formats consistently outperformed both the fixed-point baseline and the alternative custom design in terms of fidelity, and was therefore selected as the new numerical standard for the emulator architecture. |
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Relatori: | Maurizio Zamboni, Giovanna Turvani, Mariagrazia Graziano |
Anno accademico: | 2024/25 |
Tipo di pubblicazione: | Elettronica |
Numero di pagine: | 111 |
Soggetti: | |
Corso di laurea: | Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering) |
Classe di laurea: | Nuovo ordinamento > Laurea magistrale > LM-29 - INGEGNERIA ELETTRONICA |
Aziende collaboratrici: | Politecnico di Torino |
URI: | http://webthesis.biblio.polito.it/id/eprint/36521 |
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