Improved robustness of FPGA dataflow accelerators for Convolutional Neural Networks

Neural Networks are computational models that excel at recognizing patterns and extracting meaningful insights from data. Today they have become a pillar of modern technology, powering applications in diverse domains such as image recognition, autonomous driving, and medical diagnostics. As neural networks find their way into safety-critical fields, such as healthcare, aerospace, and automotive systems, the demand for fast, efficient, and reliable inference grows significantly. Moreover, deploying these networks on edge devices, such as IoT sensors, or embedded systems, presents additional challenges due to their limited computational resources and power constraints. To address these challenges, it becomes essential to reduce the size and complexity of neural networks without compromising their performance. Techniques like model quantization and pruning are vital in achieving this balance. To meet the increasing demand for deploying neural networks in safety-critical and resource-constrained environments, it is also crucial to ensure their reliability and robustness. This is particularly important for edge devices, where hardware vulnerabilities, such as bit-flip errors and external attacks, can significantly impact the performance and safety of the deployed systems. The objective of this thesis is to enhance the robustness of FPGA dataflow accelerators for Convolutional Neural Networks (CNNs) against hardware bit-flip errors. Bit-flips caused by electromagnetic interference or cosmic rays, can corrupt the weights, activations, or other intermediate data in the accelerator pipeline, leading to incorrect predictions that could have severe and possibly life-threatening consequences. This research focuses on Fault-Aware Training (FAT), a technique that involves simulating various types of hardware faults during the training process, resulting in a model inherently robust to faults and potentially reducing the need for expensive redundancy mechanisms. This approach is applied to quantized neural networks, which have been discretized using the Brevitas framework. The primary contribution of this thesis is the development of the bit-flip error model. A custom error injection layer has been developed, integrated with Brevitas, to enable the simulation of bit-flip faults injected randomly in the activations during training and inference. This layer provides a critical tool for evaluating and improving the fault tolerance of neural networks. Another contribution is the development of the Fault-Aware Fine-Tuning (FAFT) methodology which is an extension to the already well known Fault-Aware Training (FAT) procedure. The FAT training technique has been enhanced to support pretrained quantized neural networks, eliminating the need to train models from scratch. This improvement also enables the method to handle a wide range of error injection probabilities without compromising the stability of the training process. Finally, the fine-tuned model was exported and deployed on the Xilinx ZCU102 FPGA accelerator board using the FINN framework. The resilience of these networks has been rigorously evaluated by comparing the fault tolerance observed in software simulations with the behavior on actual hardware. Experimental results demonstrate that the fault-aware fine-tuned network exhibits significant resilience to bit-flip errors in both software and hardware simulations.