Optimizing Cell-Aware Testing: Methodologies for Stress and Defect-Oriented Testing in Modern Electronic Devices

As the complexity and size of modern electronic devices increase, it becomes increasingly difficult to fully cover the different types of defects that can occur. In particular, with new technologies, intra-cell defects have become vital. For this reason, cell-aware testing has recently been added to traditional processes to achieve desired levels of quality. This thesis proposes new methodologies to optimize cell-aware testing in two different but equally significant contexts in the modern approach to testing both safety-critical and non-safety-critical devices. The first context analyzed is Cell-Aware Stress Testing. This testing method is becoming increasingly important to excite potential latent defects that may occur inside the device cells. This process is necessary to reduce the infant mortality of integrated circuits and to ensure the required device reliability. For Cell-Aware Stress Testing the research is conducted based on the Cell-Aware Transistor State Model proposed by Stephan Eggersgluß and Andreas Glowatz in IEEE International Test Conference 2024, which stands out from the state of the art as the first methodology to create a stress view for cell libraries and an application flow to determine the quality of stress patterns. On top of this the thesis proposes algorithmic solutions to reduce the number of patterns required to obtain sufficient stress activity on each transistor contained in the cell. By using tools such as SAT Solvers and Integer Linear Programming Solvers, and reformulating the problem appropriately, it is shown that a 75% reduction in the number of patterns and a factor of 3 increase in the number of Don't-Cares terms can be achieved within an acceptable timeframe. In this way, it is possible to guarantee minimal computational and testing costs and a sufficient degree of freedom in pattern generation for the ATPG. The second context analyzed is Defect-Oriented Cell-Aware Testing. This testing model aims to obtain very high fault coverage by directly targeting layout-based intra-cell faults. For Defect-Oriented Cell-Aware Testing the thesis proposes an algorithmic methodology to guide the automatic pattern generation with the aim of reducing the number of patterns generated and consequently the final test time and the generation runtime. This is performed by exploiting weak detection to recognize new equivalent defects and to improve the number of Don't-Cares terms. The downside is a general reduction in the impact of final test patterns, but this problem is addressed by giving the user the possibility of choosing the accepted trade-off between the parameters in play. By making use of well-known algorithms such as Quine-McCluskey and custom, ad-hoc algorithms for the problem, improvements in terms of the number of patterns and the number of Don't-Cares terms of between 1% and 5% can be observed, depending on the cell analyzed and the fault model considered. In the case study, the fault models analyzed are One Time Frame (1TF) and Two Time Frame (2TF).