Development of a UVM environment for a safety relevant block

As predicted by Moore’s law, the continuous advancements in the development of high-performance Integrated Circuits (ICs) have enabled the integration of various complex functionalities into smaller chips. However, this process has introduced new challenges in ensuring the absence of bugs that may compromise the correct functionality of the designs, making traditional verification methods insufficient for these increased levels of complexity. As a result, the Universal Verification Methodology (UVM) was developed as an industry standard with the aim of improving the verification process of digital designs. This increasing performance of ICs has led to the widespread use of electronic systems in various domains. In particular, the automotive industry was revolutionized by the use of electronics. As a matter of fact, modern vehicles rely significantly on electronic systems for multiple applications, including efficiency, safety, and comfort. Nevertheless, this extensive integration of electronic systems in vehicles brought safety challenges since hardware failures in a vehicle may lead to disastrous consequences. To minimize the risks connected to this spread of electronics use in vehicles, the International Standard Organization (ISO) introduced ISO 26262, a standard that defines guidelines for developing electronic systems for the automotive sector. This thesis examines the ISO26262 safety standard and how it is applied within a complex hardware accelerator, the Data Flow Architecture (DFA), with a particular focus on the LBIST controller, which is a safety-relevant module whose functionality will be verified using a UVM-based testbench. The development process of this testbench starts by understanding the various functionalities of the Design Under Verification (DUV). Next, its functional requirements are defined and translated into SystemVerilog covergroups. Following this, the different components of the UVM testbench are developed in a configurable and reusable perspective. Subsequently, different test sequences are defined based on how the DUV should be stimulated to reach all possible corner cases. Finally, by tuning the test sequences and consequently also the stimulus of the DUV, according to the results of the different simulations, which were analyzed not only in terms of functional correctness of the DUV operation but also in terms of reached coverage, it was possible to obtain a code coverage and functional coverage of 100 %, which confirms that the DUV has been exercised in all its possible working states. The tool used for the UVM simulations is Incisive, which is an EDA tool developed by Cadence Design Systems.