As predicted by Moore’s law, the continuous advancements in the development of high-performance Integrated Circuits (ICs) have enabled the integration of various complex functionalities into smaller chips. However, this process has introduced new challenges in ensuring the absence of bugs that may compromise the correct functionality of the designs, making traditional verification methods insufficient for these increased levels of complexity. As a result, the Universal Verification Methodology (UVM) was developed as an industry standard with the aim of improving the verification process of digital designs. This increasing performance of ICs has led to the widespread use of electronic systems in various domains.