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Electrical Characterization of Molybdenum/Silicon Carbide Schottky Barriers

Rebecca D'Amico

Electrical Characterization of Molybdenum/Silicon Carbide Schottky Barriers.

Rel. Luciano Scaltrito, Sergio Ferrero. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering), 2025

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Abstract:

This thesis project focuses on the electrical characterization of molybdenum (Mo)/silicon carbide (SiC) Schottky barriers for the development of high performance SiC-based power electronic devices. Silicon carbide is a group-IV compound semiconductor that exhibits such advantageous properties to make it a suitable candidate for high power applications. Indeed, it is characterized by a wide energy band gap: if the 4H-SiC polytype is considered, then the value of the band gap is almost three times the silicon one. High breakdown voltage, high carrier saturation velocity, small intrinsic carrier concentration and high thermal conductivity are among other SiC features that are worth mentioning. Molybdenum shows interesting properties too, being characterized by low electrical resistivity and high melting point. Barrier height and ideality factor represent two of the most important parameters that allow the electrical chacterization of Schottky diodes. From a theoretical standpoint, the Schottky barrier height of a Schottky diode is evaluated as the difference of the metal work function and the semiconductor electron affinity; however, experimental results show that it can be affected by the technological processes involved in the fabrication phase. Thus, Schottky diode structures to be characterized electrically have been fabricated on four 4H-SiC epitaxial wafers through the adoption of a process flow in which three conditions can vary in order to obtain different devices. They are the metal at the interface (Ti or Mo), the SiC surface conditioning treatment prior to the metal deposition (HF cleaning, Ar cleaning, phosphorus pentoxide deposition with a following cleaning procedure) and the barrier annealing temperature (from 500°C to 1000°C). The production has been carried out by Vishay Semiconductor Italiana. Successively, I-V measurements and C-V measurements have been performed on several devices with the aim of deriving barrier height and ideality factor values for each of them. A detailed comparison among results of measurements is then presented to determine advantages and disadvantages of diverse process conditions and identify factors limiting device performance.

Relatori: Luciano Scaltrito, Sergio Ferrero
Anno accademico: 2024/25
Tipo di pubblicazione: Elettronica
Numero di pagine: 100
Soggetti:
Corso di laurea: Corso di laurea magistrale in Ingegneria Elettronica (Electronic Engineering)
Classe di laurea: Nuovo ordinamento > Laurea magistrale > LM-29 - INGEGNERIA ELETTRONICA
Aziende collaboratrici: Vishay Semiconductor Italiana SpA
URI: http://webthesis.biblio.polito.it/id/eprint/35482
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