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Study and Development of Optimised FPGA Manufacturing Tests Using On-Board processors in Rad-Hard Reconfigurable SoCs

Arianna Valenza

Study and Development of Optimised FPGA Manufacturing Tests Using On-Board processors in Rad-Hard Reconfigurable SoCs.

Rel. Luca Sterpone. Politecnico di Torino, Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering), 2025

Abstract:

In the fast-paced landscape of the New Space Economy, companies are forced to accelerate time-to-market while keeping competitive pricing. This leads to an increasing demand for more efficient and flexible manufacturing processes, challenging traditional production methods. This thesis investigates an advanced approach to optimize the manufacturing testing procedures of Radiation Hardened by Design Field-Programmable Gate Arrays (FPGAs) embedded in System-on-Chip (SoC) devices, which can be adopted to support critical high-reliability aerospace missions and other demanding applications. The study aims to streamline traditional testing methods, which often prove complex and inflexible, by exploring the potential of using the onboard SoC processor for a light and adaptable test environment. A proof-of-concept study on NanoXplore NG-Ultra was conducted to assess the feasibility of executing FPGA functional tests directly via the on-board ARM processor, focusing the research on testing the FPGA's configuration memory, a critical and fault-sensitive component fundamental for the device reliability and its nominal functioning. The testing framework developed consists of custom FPGA functional test routines implemented as both low-level APIs for direct hardware interaction and high-level APIs for algorithmic test methods. Performance comparisons between the new processor-based approach and traditional testing show a significant storage saving, by two orders of magnitude, and slight improvements in execution time, with the latter limited by specific architectural constraints of the device. Additionally, this methodology supports online testing, a key feature for safety-critical applications, enhancing reliability during functional operations. These findings lay a foundation for the development of future SoC generations, guiding advancements in high-performance, flexible and fault-resilient devices tailored to meet the demands of the New Space Economy.

Relatori: Luca Sterpone
Anno accademico: 2024/25
Tipo di pubblicazione: Elettronica
Numero di pagine: 84
Informazioni aggiuntive: Tesi secretata. Fulltext non presente
Soggetti:
Corso di laurea: Corso di laurea magistrale in Ingegneria Informatica (Computer Engineering)
Classe di laurea: Nuovo ordinamento > Laurea magistrale > LM-32 - INGEGNERIA INFORMATICA
Ente in cotutela: Pole Universitaire Leonard de Vinci (ESILV) (FRANCIA)
Aziende collaboratrici: NON SPECIFICATO
URI: http://webthesis.biblio.polito.it/id/eprint/35358
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