On Generating Timed Behavioral Models: An Investigation of Simulation Techniques

The increasing complexity of modern hardware designs necessitates shifting from traditional Register-Transfer Level (RTL) abstractions to higher-level modeling approaches. One of these approaches, the Universal Specification Format (USF), based on metamodeling and embedded in the Python programming language, enables the uniform expression of digital hardware systems’ functional and temporal behavior. While USF models are inherently static, conventional hardware development heavily relies on simulation for tasks ranging from early validation and debugging to dynamic verification and virtual prototyping. To bridge the gap between static specifications and dynamic development needs, we present two standalone code generation approaches that transform USF models into executable behavioral models. For both, this work presents their respective implementations and concludes with a detailed comparison between both in terms of performance. The first approach implements behavioral models in RTL which enables synthesis and emulation besides execution on RTL simulators. However, the generated RTL is not optimized. When it comes to pipelined designs, a scheduler logic component is required, adding restrictions to the model. The second approach produces software-based behavioral models with a cycle-based state update. This approach further leverages dynamically allocating objects allowing for greater flexibility in the simulation environment. Both approaches are applied to the ALU model and variants hereof and other multiple concrete component specifications in the case of software-based generation flow. The Application demonstrates the feasibility and re-usability of the proposed code generators. We compare both approaches in terms of simulation performance and runtime complexity. The RTL behavioral models are further synthesized on an FPGA platform to analyze their resource requirements. Results showed trade-offs between performance and scalability as well as flexibility. The RTL models showed better performance, but worse scalability. On the other hand, SW-models utilized object-oriented programming features in SystemVerilog and dynamic allocation of objects which came in favor of flexibility and better scalability, but added performance overhead.