FPGA Acceleration in SmartNICs: Porting and Performance Evaluation of the Rosebud Framework.

Field Programmable Gate Arrays (FPGAs) have emerged as a consolidated solution to address the challenges of high-performance networking applications, used in cloud computing environments, datacenters and telecommunication in general. The usage of FPGAs as accelerators for Smart Network Interface Cards (smartNICs) provides a flexible solution for tasks that require packet processing, such as deep packet inspection and firewalls. The inherent high performance and flexibility benefits of FPGAs are further improved by FPGA virtualization technology, which enables multi-tenancy execution through the distribution of FPGA resources, and by Partial Reconfiguration, which allows dynamic resource allocation and isolation, in order to optimize hardware utilization. Today, several open-source solutions provide smartNIC functionalities to FPGAs, allowing the execution of tasks that are traditionally handled by CPUs to be offloaded to FPGA dedicated hardware accelerators. These solutions often provide network shells capable of 100Gbps+ speed, allowing the development of custom packet-processing accelerators that work on the lower layers of the network stack. However, many of these solutions lack support for hardware virtualization, leading to high virtualization overhead in software and lower hardware resource utilization. This thesis was conducted during an internship at Virtual Open Systems in Grenoble, France, a company specialized in virtualization for embedded systems and development of solutions for automotive and cloud-computing environments. The company is interested in developing an FPGA virtualization solution that enables virtual access to custom hardware accelerators. The study investigates a middlebox open-source framework, called Rosebud, designed to help the deployment of hardware accelerators, providing a high-speed network shell and a software interface to allow easy configuration and debugging of hardware accelerators. The research evaluates Rosebud’s key features and its potential for future integration of virtualization capabilities. By deploying small RISC-V CPU cores in the FPGA as control units, Rosebud enhances management of accelerators at runtime. Furthermore, Partial Reconfiguration allows accelerators to be programmed at runtime, maximizing flexibility of FPGA resources and reducing deployment time of new accelerators, which is a key problem in traditional FPGA development. A porting procedure was performed in order to support the Alveo U55C accelerator card, which was originally unsupported. The evaluation of Rosebud is performed with a custom benchmark that measures performance in a local network environment. A hardware accelerator was developed and deployed to test its impact on peak performance. The research demonstrates promising results for the use of Rosebud as a basis for a virtualized networking infrastructure.