Efficient Transfer of Event Data for Neuromorphic Applications on SoC-FPGA

This thesis aims to address the efficiency challenges in data transfer for neuromorphic hardware, which traditionally operate outside the von Neumann architecture paradigm. While neuromorphic hardware excels in mimicking biological neural networks, it still relies on von Neumann systems for data acquisition in many near-future applications. This thesis focuses on designing and implementing a Direct Memory Access (DMA) architecture tailored for neuromorphic applications in System-on-Chip (SoC) to enhance data transfer efficiency. The project specifically investigates optimizing DMA functionality to streamline the data flow between external sources and neuromorphic hardware, ultimately improving overall system performance and energy efficiency. A key aspect of the design involves double buffer ping pong mode, where one buffer is written while the other is read, ensuring continuous data flow. Performance is then compared across different transfer methods and Processing System (PS) - Programmable Logic (PL) interface ports to identify the most efficient implementation. Furthermore, different DMA modes, such as simple and ScatterGather (SG), are evaluated and benchmarked. By analyzing these various configurations, the thesis provides insights into optimizing data transfer for neuromorphic applications in SoC Field Programmable Gate Arrays (FPGA), leading to improved system performance and energy efficiency. Benchmarking demonstrated that while the High Performance (HP) port generally outperformed the other ports in simple DMA configuration, SG mode with a cyclic configuration achieved superior throughput, reaching 6 GB/s. These results highlight the crucial role of optimal DMA configuration in maximizing data transfer efficiency for neuromorphic applications in SoC.