Implementation of RISC-V Instruction Set Extensions

The term Internet of Things (IoT) indicates a network of devices connected to collect, exchange, and act on data, enabling intelligent automation and decision-making across multiple applications, including smart homes, healthcare, transportation, agriculture, and many others. At the foundation of the IoT hierarchy are endpoint devices, which integrate multiple sensors and are built around a Microcontroller Unit (MCU). Since they are typically battery-powered, it is essential to limit the power consumption to extend the battery lifetime. In fact, the MCU is very often based on a low-power Central Processing Unit (CPU). However, this implies that the role of the MCU is limited to controlling and lightweight processing, and a lot of raw data are sent throughout the IoT hierarchy. As communication with higher-level nodes demands significant power, reducing the amount of transmitted data is crucial. In this context, the edge-computing paradigm comes into play, where these end-point devices evolve from simple data collectors to smart devices able to perform complex near-sensor processing such as feature extraction, recognition, and classification. Consequently, the information transmitted is denser, the communication time is reduced, and substantial power savings are achieved. In this thesis, a RISC-V-based system was designed. It consists of the CV32E20 core by the OpenHW group and a coprocessor, which communicates via the Core-V eXtension interface (CV-X-IF). The CV32E20 was enhanced with the Post-Increment Load and Store and Hardware Loop ISA extensions, whereas the coprocessor implements an additional ISA extension that includes complex arithmetic functions, fixed-point arithmetic support, and Single Instruction Multiple Data (SIMD) instructions. These extensions were implemented to improve performance at the price of a small increase in the area and power consumption for a major gain in energy efficiency.